[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformPkg.fdf

#/** @file\r
# FDF file of Platform.\r
#\r
# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials are licensed and made available under\r
# the terms and conditions of the BSD License that accompanies this distribution.\r
# The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php.\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#\r
#**/\r
\r
[Defines]\r
DEFINE FLASH_BASE       = 0xFFC00000     #The base address of the 4Mb FLASH Device.\r
DEFINE FLASH_SIZE       = 0x00400000     #The flash size in bytes of the 4Mb FLASH Device.\r
DEFINE FLASH_BLOCK_SIZE = 0x1000        #The block size in bytes of the 4Mb FLASH Device.\r
DEFINE FLASH_NUM_BLOCKS = 0x400           #The number of blocks in 4Mb FLASH Device.\r
DEFINE FLASH_AREA_BASE_ADDRESS                                = 0xFF800000\r
DEFINE FLASH_AREA_SIZE                                        = 0x00800000\r
\r
DEFINE FLASH_REGION_VLVMICROCODE_OFFSET                       = 0x00000000\r
DEFINE FLASH_REGION_VLVMICROCODE_SIZE                         = 0x00040000\r
DEFINE FLASH_REGION_VLVMICROCODE_BASE                         = 0xFFC00000\r
\r
DEFINE FLASH_REGION_VPD_OFFSET                                = 0x00040000\r
DEFINE FLASH_REGION_VPD_SIZE                                  = 0x0003E000\r
\r
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0007E000\r
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE   = 0x00002000\r
\r
\r
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET   = 0x00080000\r
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE     = 0x00040000\r
\r
!if $(MINNOW2_FSP_BUILD) == TRUE\r
DEFINE FLASH_REGION_FSPBIN_OFFSET                             = 0x000C0000\r
DEFINE FLASH_REGION_FSPBIN_SIZE                               = 0x00048000\r
DEFINE FLASH_REGION_FSPBIN_BASE                               = 0xFFCC0000\r
\r
DEFINE FLASH_REGION_AZALIABIN_OFFSET                          = 0x00108000\r
DEFINE FLASH_REGION_AZALIABIN_SIZE                            = 0x00008000\r
DEFINE FLASH_REGION_AZALIABIN_BASE                            = 0xFFD08000\r
\r
!endif\r
\r
DEFINE FLASH_REGION_FVMAIN_OFFSET                             = 0x00110000\r
DEFINE FLASH_REGION_FVMAIN_SIZE                               = 0x00210000\r
\r
DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET                       = 0x00320000\r
DEFINE FLASH_REGION_FV_RECOVERY2_SIZE                         = 0x00070000\r
\r
DEFINE FLASH_REGION_FV_RECOVERY_OFFSET                        = 0x00390000\r
DEFINE FLASH_REGION_FV_RECOVERY_SIZE                          = 0x00070000\r
\r
################################################################################\r
#\r
# FD Section\r
# The [FD] Section is made up of the definition statements and a\r
# description of what goes into  the Flash Device Image.  Each FD section\r
# defines one flash "device" image.  A flash device image may be one of\r
# the following: Removable media bootable image (like a boot floppy\r
# image,) an Option ROM image (that would be "flashed" into an add-in\r
# card,) a System "Flash"  image (that would be burned into a system's\r
# flash) or an Update ("Capsule") image that will be used to update and\r
# existing system flash.\r
#\r
################################################################################\r
[FD.Vlv]\r
BaseAddress   = $(FLASH_BASE)|gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of the 3Mb FLASH Device.\r
Size          = $(FLASH_SIZE)|gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize        #The flash size in bytes of the 3Mb FLASH Device.\r
ErasePolarity = 1\r
BlockSize     = $(FLASH_BLOCK_SIZE)          #The block size in bytes of the 3Mb FLASH Device.\r
NumBlocks     = $(FLASH_NUM_BLOCKS)          #The number of blocks in 3Mb FLASH Device.\r
\r
#\r
#Flash location override based on actual flash map\r
#\r
SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress            = $(FLASH_AREA_BASE_ADDRESS)\r
SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize                   = $(FLASH_AREA_SIZE)\r
\r
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(FLASH_REGION_VLVMICROCODE_BASE) + 0x60\r
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(FLASH_REGION_VLVMICROCODE_SIZE) - 0x60\r
\r
!if $(MINNOW2_FSP_BUILD) == TRUE\r
# put below PCD value setting into dsc file\r
#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress                = $(FLASH_REGION_VLVMICROCODE_BASE)\r
#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize             = $(FLASH_REGION_VLVMICROCODE_SIZE)\r
#SET gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset                    = 0x60\r
#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress                   = $(FLASH_AREA_BASE_ADDRESS)\r
#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize                      = $(FLASH_AREA_SIZE)\r
#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase                          = $(FLASH_REGION_FSPBIN_BASE)\r
#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize                          = $(FLASH_REGION_FSPBIN_SIZE)\r
\r
!endif\r
################################################################################\r
#\r
# Following are lists of FD Region layout which correspond to the locations of different\r
# images within the flash device.\r
#\r
# Regions must be defined in ascending order and may not overlap.\r
#\r
# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
# "0x" characters. Like:\r
# Offset|Size\r
# PcdOffsetCName|PcdSizeCName\r
# RegionType <FV, DATA, or FILE>\r
# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000, and FV_RECOVERY can be enlarged to 0x80000\r
#\r
################################################################################\r
  #\r
  # CPU Microcodes\r
  #\r
\r
$(FLASH_REGION_VLVMICROCODE_OFFSET)|$(FLASH_REGION_VLVMICROCODE_SIZE)\r
gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize\r
FV = MICROCODE_FV\r
$(FLASH_REGION_VPD_OFFSET)|$(FLASH_REGION_VPD_SIZE)\r
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
#NV_VARIABLE_STORE\r
DATA = {\r
  ## This is the EFI_FIRMWARE_VOLUME_HEADER\r
  # ZeroVector []\r
  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
  # FileSystemGuid: gEfiSystemNvDataFvGuid         =\r
  #  { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}\r
  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,\r
  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,\r
  # FvLength: 0x80000\r
  0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,\r
  #Signature "_FVH"       #Attributes\r
  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,\r
  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision\r
  0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02,\r
  #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block\r
  0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,\r
  #Blockmap[1]: End\r
  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
  ## This is the VARIABLE_STORE_HEADER\r
!if $(SECURE_BOOT_ENABLE) == TRUE\r
  #Signature: gEfiAuthenticatedVariableGuid =\r
  #  { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}\r
  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,\r
  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,\r
!else\r
  #Signature: gEfiVariableGuid =\r
  #  { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}\r
  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,\r
  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,\r
!endif\r
  #Size: 0x3E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x03DFB8\r
  # This can speed up the Variable Dispatch a bit.\r
  0xB8, 0xDF, 0x03, 0x00,\r
  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32\r
  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
}\r
\r
\r
$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE)\r
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize\r
#NV_FTW_WORKING\r
DATA = {\r
  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid         =\r
  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}\r
  0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,\r
  0xA0, 0xCE, 0x65, 0x0,  0xFD, 0x9F, 0x1B, 0x95,\r
\r
  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved\r
  0xE2, 0x33, 0xF2, 0x3,  0xFE, 0xFF, 0xFF, 0xFF,\r
  # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0\r
  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
}\r
\r
$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE)\r
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
\r
!if $(MINNOW2_FSP_BUILD) == TRUE\r
\r
  $(FLASH_REGION_FSPBIN_OFFSET)|$(FLASH_REGION_FSPBIN_SIZE)\r
  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize\r
  FILE = Vlv2MiscBinariesPkg/FspBinary/FvFsp.bin\r
\r
\r
  $(FLASH_REGION_AZALIABIN_OFFSET)|$(FLASH_REGION_AZALIABIN_SIZE)\r
  FILE = Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin\r
\r
!endif\r
\r
  #\r
  # Main Block\r
  #\r
$(FLASH_REGION_FVMAIN_OFFSET)|$(FLASH_REGION_FVMAIN_SIZE)\r
gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize\r
FV = FVMAIN_COMPACT\r
\r
  #\r
  # FV Recovery#2\r
  #\r
$(FLASH_REGION_FV_RECOVERY2_OFFSET)|$(FLASH_REGION_FV_RECOVERY2_SIZE)\r
gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size\r
FV = FVRECOVERY2\r
\r
  #\r
  # FV Recovery\r
  #\r
$(FLASH_REGION_FV_RECOVERY_OFFSET)|$(FLASH_REGION_FV_RECOVERY_SIZE)\r
gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize\r
FV = FVRECOVERY\r
\r
################################################################################\r
#\r
# FV Section\r
#\r
# [FV] section is used to define what components or modules are placed within a flash\r
# device file.  This section also defines order the components and modules are positioned\r
# within the image.  The [FV] section consists of define statements, set statements and\r
# module statements.\r
#\r
################################################################################\r
[FV.MICROCODE_FV]\r
BlockSize          = $(FLASH_BLOCK_SIZE)\r
FvAlignment        = 16\r
ERASE_POLARITY     = 1\r
MEMORY_MAPPED      = TRUE\r
STICKY_WRITE       = TRUE\r
LOCK_CAP           = TRUE\r
LOCK_STATUS        = FALSE\r
WRITE_DISABLED_CAP = TRUE\r
WRITE_ENABLED_CAP  = TRUE\r
WRITE_STATUS       = TRUE\r
WRITE_LOCK_CAP     = TRUE\r
WRITE_LOCK_STATUS  = TRUE\r
READ_DISABLED_CAP  = TRUE\r
READ_ENABLED_CAP   = TRUE\r
READ_STATUS        = TRUE\r
READ_LOCK_CAP      = TRUE\r
READ_LOCK_STATUS   = TRUE\r
\r
FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {\r
  $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITECTURE)/MicrocodeUpdates.bin\r
}\r
\r
!if $(RECOVERY_ENABLE)\r
[FV.FVRECOVERY_COMPONENTS]\r
FvAlignment        = 16         #FV alignment and FV attributes setting.\r
ERASE_POLARITY     = 1\r
MEMORY_MAPPED      = TRUE\r
STICKY_WRITE       = TRUE\r
LOCK_CAP           = TRUE\r
LOCK_STATUS        = TRUE\r
WRITE_DISABLED_CAP = TRUE\r
WRITE_ENABLED_CAP  = TRUE\r
WRITE_STATUS       = TRUE\r
WRITE_LOCK_CAP     = TRUE\r
WRITE_LOCK_STATUS  = TRUE\r
READ_DISABLED_CAP  = TRUE\r
READ_ENABLED_CAP   = TRUE\r
READ_STATUS        = TRUE\r
READ_LOCK_CAP      = TRUE\r
READ_LOCK_STATUS   = TRUE\r
\r
INF  RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchUsb.inf\r
INF  MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf\r
INF  MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf\r
INF  MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf\r
INF  FatPkg/FatPei/FatPei.inf\r
INF  MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf\r
INF  SignedCapsulePkg/Universal/RecoveryModuleLoadPei/RecoveryModuleLoadPei.inf\r
!endif\r
\r
################################################################################\r
#\r
# FV Section\r
#\r
# [FV] section is used to define what components or modules are placed within a flash\r
# device file.  This section also defines order the components and modules are positioned\r
# within the image.  The [FV] section consists of define statements, set statements and\r
# module statements.\r
#\r
################################################################################\r
[FV.FVRECOVERY2]\r
BlockSize          = $(FLASH_BLOCK_SIZE)\r
FvAlignment        = 16         #FV alignment and FV attributes setting.\r
ERASE_POLARITY     = 1\r
MEMORY_MAPPED      = TRUE\r
STICKY_WRITE       = TRUE\r
LOCK_CAP           = TRUE\r
LOCK_STATUS        = TRUE\r
WRITE_DISABLED_CAP = TRUE\r
WRITE_ENABLED_CAP  = TRUE\r
WRITE_STATUS       = TRUE\r
WRITE_LOCK_CAP     = TRUE\r
WRITE_LOCK_STATUS  = TRUE\r
READ_DISABLED_CAP  = TRUE\r
READ_ENABLED_CAP   = TRUE\r
READ_STATUS        = TRUE\r
READ_LOCK_CAP      = TRUE\r
READ_LOCK_STATUS   = TRUE\r
FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092\r
\r
\r
\r
INF $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf\r
\r
!if $(MINNOW2_FSP_BUILD) == FALSE\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf\r
INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf\r
INF EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf\r
!endif\r
\r
# INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PiSmmCommunicationPei.inf\r
!if $(TPM_ENABLED) == TRUE\r
INF SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf\r
INF SecurityPkg/Tcg/TcgPei/TcgPei.inf\r
INF SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf\r
!endif\r
!if $(FTPM_ENABLE) == TRUE\r
INF  SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf #use PCD config\r
!endif\r
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
\r
!if $(ACPI50_ENABLE) == TRUE\r
 INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf\r
!endif\r
!if $(PERFORMANCE_ENABLE) == TRUE\r
INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf\r
!endif\r
\r
!if $(RECOVERY_ENABLE)\r
FILE FV_IMAGE = 1E9D7604-EF45-46a0-BD8A-71AC78C17AC1 {\r
  SECTION PEI_DEPEX_EXP = {gEfiPeiMemoryDiscoveredPpiGuid AND gEfiPeiBootInRecoveryModePpiGuid}\r
  SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF {    # LZMA COMPRESS GUID\r
    SECTION FV_IMAGE = FVRECOVERY_COMPONENTS\r
  }\r
}\r
!endif\r
\r
[FV.FVRECOVERY]\r
BlockSize          = $(FLASH_BLOCK_SIZE)\r
FvAlignment        = 16         #FV alignment and FV attributes setting.\r
ERASE_POLARITY     = 1\r
MEMORY_MAPPED      = TRUE\r
STICKY_WRITE       = TRUE\r
LOCK_CAP           = TRUE\r
LOCK_STATUS        = TRUE\r
WRITE_DISABLED_CAP = TRUE\r
WRITE_ENABLED_CAP  = TRUE\r
WRITE_STATUS       = TRUE\r
WRITE_LOCK_CAP     = TRUE\r
WRITE_LOCK_STATUS  = TRUE\r
READ_DISABLED_CAP  = TRUE\r
READ_ENABLED_CAP   = TRUE\r
READ_STATUS        = TRUE\r
READ_LOCK_CAP      = TRUE\r
READ_LOCK_STATUS   = TRUE\r
FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270091\r
\r
\r
!if $(MINNOW2_FSP_BUILD) == TRUE\r
INF IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf\r
!else\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf\r
!endif\r
\r
INF MdeModulePkg/Core/Pei/PeiMain.inf\r
!if $(MINNOW2_FSP_BUILD) == TRUE\r
INF Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf\r
INF IntelFspWrapperPkg/FspInitPei/FspInitPei.inf\r
!endif\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf\r
INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf\r
INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
\r
INF $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf\r
\r
!if $(MINNOW2_FSP_BUILD) == FALSE\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf\r
!endif\r
\r
!if $(FTPM_ENABLE) == TRUE\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/fTPMInitPeim.inf\r
!endif\r
\r
!if $(SOURCE_DEBUG_ENABLE) == TRUE\r
  INF  SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf\r
!endif\r
\r
\r
!if $(CAPSULE_ENABLE) == TRUE\r
INF  MdeModulePkg/Universal/CapsulePei/CapsulePei.inf\r
!if $(DXE_ARCHITECTURE) == "X64"\r
INF  MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf\r
!endif\r
!endif\r
\r
!if $(MINNOW2_FSP_BUILD) == FALSE\r
!if $(PCIESC_ENABLE) == TRUE\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf\r
!endif\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf\r
!endif\r
\r
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
\r
[FV.FVMAIN]\r
BlockSize          = $(FLASH_BLOCK_SIZE)\r
FvAlignment        = 16\r
ERASE_POLARITY     = 1\r
MEMORY_MAPPED      = TRUE\r
STICKY_WRITE       = TRUE\r
LOCK_CAP           = TRUE\r
LOCK_STATUS        = TRUE\r
WRITE_DISABLED_CAP = TRUE\r
WRITE_ENABLED_CAP  = TRUE\r
WRITE_STATUS       = TRUE\r
WRITE_LOCK_CAP     = TRUE\r
WRITE_LOCK_STATUS  = TRUE\r
READ_DISABLED_CAP  = TRUE\r
READ_ENABLED_CAP   = TRUE\r
READ_STATUS        = TRUE\r
READ_LOCK_CAP      = TRUE\r
READ_LOCK_STATUS   = TRUE\r
FvNameGuid         = A881D567-6CB0-4eee-8435-2E72D33E45B5\r
\r
APRIORI DXE {\r
  INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
  INF  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf\r
  INF  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf\r
  }\r
\r
FILE FREEFORM = C3E36D09-8294-4b97-A857-D5288FE33E28 {\r
    SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITECTURE)/BiosId.bin\r
  }\r
\r
  #\r
  # EDK II Related Platform codes\r
  #\r
\r
  !if $(MINNOW2_FSP_BUILD) == TRUE\r
  INF IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf\r
  !endif\r
\r
INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
!if $(ACPI50_ENABLE) == TRUE\r
INF  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf\r
INF  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf\r
!endif\r
\r
\r
INF IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf\r
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r
INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf\r
INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf\r
INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf\r
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf\r
INF $(PLATFORM_PACKAGE)/Metronome/Metronome.inf\r
INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
INF USE=X64 MdeModulePkg/Logo/Logo.inf\r
INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
INF IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf\r
\r
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf\r
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf\r
INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf\r
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf\r
!if $(SECURE_BOOT_ENABLE)\r
INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf\r
!endif\r
\r
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
\r
INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf\r
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf\r
\r
\r
INF $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf\r
\r
!if $(DATAHUB_ENABLE) == TRUE\r
INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf\r
!endif\r
INF IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf\r
INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf\r
\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf\r
\r
  #\r
  # EDK II Related Silicon codes\r
  #\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf\r
\r
!if $(USE_HPET_TIMER) == TRUE\r
INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf\r
!else\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf\r
!endif\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf\r
\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf\r
\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf\r
\r
!if $(MINNOW2_FSP_BUILD) == FALSE\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf\r
!endif\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf\r
!if $(PCIESC_ENABLE) == TRUE\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf\r
!endif\r
\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf\r
!if $(MINNOW2_FSP_BUILD) == FALSE\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf\r
!else\r
INF IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf\r
INF Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf\r
!endif\r
!if $(MINNOW2_FSP_BUILD) == FALSE\r
  !if $(SEC_ENABLE) == TRUE\r
  INF  RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/HeciDrv.inf\r
  INF  RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SeCPolicyInitDxe.inf\r
  !endif\r
!endif\r
!if $(TPM_ENABLED) == TRUE\r
INF SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf\r
INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf\r
INF RuleOverride = DRIVER_ACPITABLE SecurityPkg/Tcg/TcgSmm/TcgSmm.inf\r
!endif\r
!if $(FTPM_ENABLE) == TRUE\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/Tpm2DeviceSeCPei.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Tpm2DeviceSeCDxe.inf\r
INF SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf\r
INF SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/FtpmSmm.inf\r
!endif\r
\r
#\r
# EDK II Related Platform codes\r
#\r
INF $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf\r
INF $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf\r
INF $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf\r
INF $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf\r
INF $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf\r
INF $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf\r
INF $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf\r
INF $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf\r
!if $(GOP_DRIVER_ENABLE) == TRUE\r
 INF $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf\r
 FILE DRIVER = FF0C8745-3270-4439-B74F-3E45F8C77064 {\r
  SECTION DXE_DEPEX_EXP = {gPlatformGOPPolicyGuid}\r
  SECTION PE32 = Vlv2MiscBinariesPkg/GOP/7.2.1011/RELEASE_VS2008x86/$(DXE_ARCHITECTURE)/IntelGopDriver.efi\r
  SECTION UI = "IntelGopDriver"\r
}\r
!endif\r
\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf\r
  #\r
  # SMM\r
  #\r
INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf\r
INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf\r
INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf\r
\r
INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf\r
INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf\r
INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf\r
INF $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf\r
\r
#\r
# Remove the following two SMM binary modules that prevent platform from booting to UEFI Shell\r
#\r
#INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf\r
#INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/DigitalThermalSensor.inf\r
\r
  #\r
  # ACPI\r
  #\r
INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf\r
INF $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf\r
INF IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf\r
INF RuleOverride = ACPITABLE2 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf\r
\r
INF RuleOverride = ACPITABLE $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf\r
\r
INF $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf\r
\r
INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf\r
\r
  #\r
  # PCI\r
  #\r
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf\r
\r
\r
#\r
# ISA\r
#\r
INF $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf\r
INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf\r
INF IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf\r
!if $(SOURCE_DEBUG_ENABLE) != TRUE\r
INF  IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf\r
!endif\r
#INF IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf\r
#INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf\r
\r
#\r
# SDIO\r
#\r
#INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcHost.inf\r
#INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcMediaDevice.inf\r
#\r
# IDE/SCSI/AHCI\r
#\r
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
\r
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
\r
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
!if $(SATA_ENABLE) == TRUE\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf\r
#\r
\r
#\r
INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf\r
INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf\r
!if $(SCSI_ENABLE) == TRUE\r
INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
!endif\r
#\r
!endif\r
# Console\r
#\r
INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
INF IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf\r
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
  #\r
  # USB\r
  #\r
!if $(USB_ENABLE) == TRUE\r
INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf\r
INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf\r
INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf\r
!endif\r
\r
  #\r
  #  ECP\r
  #\r
INF EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf\r
INF EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf\r
INF EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf\r
INF EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf\r
INF EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf\r
INF EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf\r
  #\r
  # SMBIOS\r
  #\r
INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf\r
INF $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf\r
\r
INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf\r
\r
  #\r
  # Legacy Modules\r
  #\r
INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf\r
\r
#\r
# FAT file system\r
#\r
INF FatPkg/EnhancedFatDxe/Fat.inf\r
\r
#\r
# UEFI Shell\r
#\r
INF  ShellPkg/Application/Shell/Shell.inf\r
\r
#\r
# dp command\r
#\r
!if $(PERFORMANCE_ENABLE) == TRUE\r
INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf\r
!endif\r
\r
!if $(GOP_DRIVER_ENABLE) == TRUE\r
FILE FREEFORM = 878AC2CC-5343-46F2-B563-51F89DAF56BA {\r
  SECTION RAW = Vlv2MiscBinariesPkg/GOP/7.2.1011/VBT/MNW2/Vbt.bin\r
  SECTION UI = "IntelGopVbt"\r
}\r
!endif\r
\r
#\r
# Network Modules\r
#\r
!if $(NETWORK_ENABLE) == TRUE\r
  FILE DRIVER = 22DE1691-D65D-456a-993E-A253DD1F308C {\r
    SECTION PE32 = Vlv2MiscBinariesPkg/UNDI/RtkUndiDxe/$(DXE_ARCHITECTURE)/RtkUndiDxe.efi\r
    SECTION UI = "UNDI"\r
  }\r
  INF  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf\r
  INF  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf\r
  INF  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf\r
  INF  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf\r
  INF  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf\r
  INF  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf\r
  INF  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf\r
  INF  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf\r
  INF  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf\r
  INF  NetworkPkg/TcpDxe/TcpDxe.inf\r
  !if $(NETWORK_IP6_ENABLE) == TRUE\r
  INF  NetworkPkg/Ip6Dxe/Ip6Dxe.inf\r
  INF  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf\r
  INF  NetworkPkg/IpSecDxe/IpSecDxe.inf\r
  INF  NetworkPkg/Udp6Dxe/Udp6Dxe.inf\r
  INF  NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf\r
  !endif\r
  !if $(NETWORK_VLAN_ENABLE) == TRUE\r
  INF  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf\r
  !endif\r
  !if $(NETWORK_ISCSI_ENABLE) == TRUE\r
    INF  NetworkPkg/IScsiDxe/IScsiDxe.inf\r
  !endif\r
!endif\r
\r
!if $(CAPSULE_ENABLE)\r
INF  MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf\r
\r
#\r
# Minnow Max System Firmware FMP\r
#\r
INF  FILE_GUID = $(FMP_MINNOW_MAX_SYSTEM) FmpDevicePkg/FmpDxe/FmpDxe.inf\r
\r
#\r
# Sample Device FMP\r
#\r
INF  FILE_GUID = $(FMP_GREEN_SAMPLE_DEVICE) FmpDevicePkg/FmpDxe/FmpDxe.inf\r
INF  FILE_GUID = $(FMP_BLUE_SAMPLE_DEVICE)  FmpDevicePkg/FmpDxe/FmpDxe.inf\r
INF  FILE_GUID = $(FMP_RED_SAMPLE_DEVICE)   FmpDevicePkg/FmpDxe/FmpDxe.inf\r
\r
!endif\r
\r
!if $(MICOCODE_CAPSULE_ENABLE)\r
INF  IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDxe.inf\r
!endif\r
\r
!if $(RECOVERY_ENABLE)\r
FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiRsa2048Sha256TestPublicKeyFileGuid) {\r
     SECTION RAW = BaseTools/Source/Python/Rsa2048Sha256Sign/TestSigningPublicKey.bin\r
     SECTION UI = "Rsa2048Sha256TestSigningPublicKey"\r
     }\r
!endif\r
\r
[FV.FVMAIN_COMPACT]\r
BlockSize          = $(FLASH_BLOCK_SIZE)\r
FvAlignment        = 16\r
ERASE_POLARITY     = 1\r
MEMORY_MAPPED      = TRUE\r
STICKY_WRITE       = TRUE\r
LOCK_CAP           = TRUE\r
LOCK_STATUS        = TRUE\r
WRITE_DISABLED_CAP = TRUE\r
WRITE_ENABLED_CAP  = TRUE\r
WRITE_STATUS       = TRUE\r
WRITE_LOCK_CAP     = TRUE\r
WRITE_LOCK_STATUS  = TRUE\r
READ_DISABLED_CAP  = TRUE\r
READ_ENABLED_CAP   = TRUE\r
READ_STATUS        = TRUE\r
READ_LOCK_CAP      = TRUE\r
READ_LOCK_STATUS   = TRUE\r
\r
\r
\r
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
!if $(LZMA_ENABLE) == TRUE\r
# LZMA Compress\r
       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
          SECTION FV_IMAGE = FVMAIN\r
       }\r
!else\r
!if $(DXE_COMPRESS_ENABLE) == TRUE\r
# Tiano Compress\r
       SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
          SECTION FV_IMAGE = FVMAIN\r
       }\r
!else\r
# No Compress\r
       SECTION COMPRESS PI_NONE {\r
          SECTION FV_IMAGE = FVMAIN\r
       }\r
!endif\r
!endif\r
     }\r
\r
[FV.SETUP_DATA]\r
BlockSize          = $(FLASH_BLOCK_SIZE)\r
#NumBlocks         = 0x10\r
FvAlignment        = 16\r
ERASE_POLARITY     = 1\r
MEMORY_MAPPED      = TRUE\r
STICKY_WRITE       = TRUE\r
LOCK_CAP           = TRUE\r
LOCK_STATUS        = TRUE\r
WRITE_DISABLED_CAP = TRUE\r
WRITE_ENABLED_CAP  = TRUE\r
WRITE_STATUS       = TRUE\r
WRITE_LOCK_CAP     = TRUE\r
WRITE_LOCK_STATUS  = TRUE\r
READ_DISABLED_CAP  = TRUE\r
READ_ENABLED_CAP   = TRUE\r
READ_STATUS        = TRUE\r
READ_LOCK_CAP      = TRUE\r
READ_LOCK_STATUS   = TRUE\r
\r
################################################################################\r
#\r
# Rules are use with the [FV] section's module INF type to define\r
# how an FFS file is created for a given INF file. The following Rule are the default\r
# rules for the different module type. User can add the customized rules to define the\r
# content of the FFS file.\r
#\r
################################################################################\r
[Rule.Common.SEC]\r
  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
    PE32  PE32    Align = 8       $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    RAW BIN       Align = 16      |.com\r
  }\r
\r
[Rule.Common.SEC.BINARY]\r
  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
    PE32  PE32    Align = 8       |.efi\r
    RAW BIN       Align = 16      |.com\r
  }\r
\r
[Rule.Common.PEI_CORE]\r
  FILE PEI_CORE = $(NAMED_GUID)            {\r
    PE32       PE32    Align = Auto      $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI       STRING="$(MODULE_NAME)" Optional\r
    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.PEIM]\r
  FILE PEIM = $(NAMED_GUID) {\r
     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex\r
     PE32        PE32   Align = Auto     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
     UI        STRING="$(MODULE_NAME)" Optional\r
     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.PEIM.BINARY]\r
  FILE PEIM = $(NAMED_GUID) {\r
     PEI_DEPEX PEI_DEPEX Optional        |.depex\r
     PE32        PE32   Align = Auto     |.efi\r
     UI        STRING="$(MODULE_NAME)" Optional\r
     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.PEIM.BIOSID]\r
  FILE PEIM = $(NAMED_GUID) {\r
     RAW       BIN                       BiosId.bin\r
     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex\r
     PE32        PE32   Align = Auto     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
     UI        STRING="$(MODULE_NAME)" Optional\r
     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.USER_DEFINED.APINIT]\r
  FILE RAW = $(NAMED_GUID) Fixed Align=4K {\r
     RAW SEC_BIN |.com\r
     }\r
#cjia 2011-07-21\r
[Rule.Common.USER_DEFINED.LEGACY16]\r
  FILE FREEFORM = $(NAMED_GUID) {\r
     UI  STRING="$(MODULE_NAME)" Optional\r
     RAW BIN |.bin\r
     }\r
#cjia\r
\r
[Rule.Common.USER_DEFINED.ASM16]\r
  FILE FREEFORM = $(NAMED_GUID) {\r
     UI  STRING="$(MODULE_NAME)" Optional\r
     RAW BIN |.com\r
   }\r
\r
[Rule.Common.DXE_CORE]\r
  FILE DXE_CORE = $(NAMED_GUID) {\r
    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.UEFI_DRIVER]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.UEFI_DRIVER.BINARY]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       |.depex\r
    PE32      PE32                     |.efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.UEFI_DRIVER.NATIVE_BINARY]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional      $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.depex\r
    PE32      PE32                    |.efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.DXE_DRIVER]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.DXE_DRIVER.BINARY]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       |.depex\r
    PE32      PE32                     |.efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.DXE_DRIVER.DRIVER_ACPITABLE]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
    RAW ACPI  Optional                |.acpi\r
    RAW ASL   Optional                |.aml\r
  }\r
\r
[Rule.Common.DXE_RUNTIME_DRIVER]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.DXE_RUNTIME_DRIVER.BINARY]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       |.depex\r
    PE32      PE32                     |.efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.DXE_SMM_DRIVER]\r
  FILE SMM = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.DXE_SMM_DRIVER.BINARY]\r
  FILE SMM = $(NAMED_GUID) {\r
    SMM_DEPEX SMM_DEPEX                |.depex\r
    PE32      PE32                     |.efi\r
    RAW       BIN  Optional            |.aml\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.DXE_SMM_DRIVER.DRIVER_ACPITABLE]\r
  FILE SMM = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
    RAW ACPI  Optional                |.acpi\r
    RAW ASL   Optional                |.aml\r
  }\r
\r
[Rule.Common.SMM_CORE]\r
  FILE SMM_CORE = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.SMM_CORE.BINARY]\r
  FILE SMM_CORE = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       |.depex\r
    PE32      PE32                     |.efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.UEFI_APPLICATION]\r
  FILE APPLICATION = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.UEFI_APPLICATION.UI]\r
  FILE APPLICATION = $(NAMED_GUID) {\r
    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI        STRING="Enter Setup"\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.USER_DEFINED]\r
  FILE FREEFORM = $(NAMED_GUID) {\r
    UI  STRING="$(MODULE_NAME)" Optional\r
    RAW BIN                |.bin\r
  }\r
\r
[Rule.Common.USER_DEFINED.BINARY]\r
  FILE FREEFORM = $(NAMED_GUID) {\r
    UI  STRING="$(MODULE_NAME)" Optional\r
    RAW BIN                |.bin\r
  }\r
\r
[Rule.Common.USER_DEFINED.ACPITABLE]\r
  FILE FREEFORM = $(NAMED_GUID) {\r
    RAW ACPI  Optional            |.acpi\r
    RAW ASL   Optional            |.aml\r
  }\r
\r
[Rule.Common.USER_DEFINED.ACPITABLE2]\r
  FILE FREEFORM = $(NAMED_GUID) {\r
    RAW ASL   Optional            |.aml\r
  }\r
\r
[Rule.Common.ACPITABLE]\r
  FILE FREEFORM = $(NAMED_GUID) {\r
    RAW ACPI  Optional            |.acpi\r
    RAW ASL   Optional            |.aml\r
  }\r
\r
[Rule.Common.PEIM.FMP_IMAGE_DESC]\r
  FILE PEIM = $(NAMED_GUID) {\r
     RAW BIN                  |.acpi\r
     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex\r
     PE32      PE32    Align=4K          $(INF_OUTPUT)/$(MODULE_NAME).efi\r
     UI       STRING="$(MODULE_NAME)" Optional\r
     VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r