ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig()

[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / CpuDxe.c

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011, ARM Limited. All rights reserved.\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "CpuDxe.h"\r
\r
#include <Guid/IdleLoopEvent.h>\r
\r
BOOLEAN                   mIsFlushingGCD;\r
\r
/**\r
  This function flushes the range of addresses from Start to Start+Length\r
  from the processor's data cache. If Start is not aligned to a cache line\r
  boundary, then the bytes before Start to the preceding cache line boundary\r
  are also flushed. If Start+Length is not aligned to a cache line boundary,\r
  then the bytes past Start+Length to the end of the next cache line boundary\r
  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r
  supported. If the data cache is fully coherent with all DMA operations, then\r
  this function can just return EFI_SUCCESS. If the processor does not support\r
  flushing a range of the data cache, then the entire data cache can be flushed.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  Start            The beginning physical address to flush from the processor's data\r
                           cache.\r
  @param  Length           The number of bytes to flush from the processor's data cache. This\r
                           function may flush more bytes than Length specifies depending upon\r
                           the granularity of the flush operation that the processor supports.\r
  @param  FlushType        Specifies the type of flush operation to perform.\r
\r
  @retval EFI_SUCCESS           The address range from Start to Start+Length was flushed from\r
                                the processor's data cache.\r
  @retval EFI_UNSUPPORTED       The processor does not support the cache flush type specified\r
                                by FlushType.\r
  @retval EFI_DEVICE_ERROR      The address range from Start to Start+Length could not be flushed\r
                                from the processor's data cache.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuFlushCpuDataCache (\r
  IN EFI_CPU_ARCH_PROTOCOL           *This,\r
  IN EFI_PHYSICAL_ADDRESS            Start,\r
  IN UINT64                          Length,\r
  IN EFI_CPU_FLUSH_TYPE              FlushType\r
  )\r
{\r
\r
  switch (FlushType) {\r
    case EfiCpuFlushTypeWriteBack:\r
      WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r
      break;\r
    case EfiCpuFlushTypeInvalidate:\r
      InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r
      break;\r
    case EfiCpuFlushTypeWriteBackInvalidate:\r
      WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r
      break;\r
    default:\r
      return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  This function enables interrupt processing by the processor.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
  @retval EFI_SUCCESS           Interrupts are enabled on the processor.\r
  @retval EFI_DEVICE_ERROR      Interrupts could not be enabled on the processor.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuEnableInterrupt (\r
  IN EFI_CPU_ARCH_PROTOCOL          *This\r
  )\r
{\r
  ArmEnableInterrupts ();\r
\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  This function disables interrupt processing by the processor.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
  @retval EFI_SUCCESS           Interrupts are disabled on the processor.\r
  @retval EFI_DEVICE_ERROR      Interrupts could not be disabled on the processor.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuDisableInterrupt (\r
  IN EFI_CPU_ARCH_PROTOCOL          *This\r
  )\r
{\r
  ArmDisableInterrupts ();\r
\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  This function retrieves the processor's current interrupt state a returns it in\r
  State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r
  are currently disabled, then FALSE is returned.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  State            A pointer to the processor's current interrupt state. Set to TRUE if\r
                           interrupts are enabled and FALSE if interrupts are disabled.\r
\r
  @retval EFI_SUCCESS           The processor's current interrupt state was returned in State.\r
  @retval EFI_INVALID_PARAMETER State is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetInterruptState (\r
  IN  EFI_CPU_ARCH_PROTOCOL         *This,\r
  OUT BOOLEAN                       *State\r
  )\r
{\r
  if (State == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  *State = ArmGetInterruptState();\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  This function generates an INIT on the processor. If this function succeeds, then the\r
  processor will be reset, and control will not be returned to the caller. If InitType is\r
  not supported by this processor, or the processor cannot programmatically generate an\r
  INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error\r
  occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  InitType         The type of processor INIT to perform.\r
\r
  @retval EFI_SUCCESS           The processor INIT was performed. This return code should never be seen.\r
  @retval EFI_UNSUPPORTED       The processor INIT operation specified by InitType is not supported\r
                                by this processor.\r
  @retval EFI_DEVICE_ERROR      The processor INIT failed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuInit (\r
  IN EFI_CPU_ARCH_PROTOCOL           *This,\r
  IN EFI_CPU_INIT_TYPE               InitType\r
  )\r
{\r
  return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
CpuRegisterInterruptHandler (\r
  IN EFI_CPU_ARCH_PROTOCOL          *This,\r
  IN EFI_EXCEPTION_TYPE             InterruptType,\r
  IN EFI_CPU_INTERRUPT_HANDLER      InterruptHandler\r
  )\r
{\r
  return RegisterInterruptHandler (InterruptType, InterruptHandler);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
CpuGetTimerValue (\r
  IN  EFI_CPU_ARCH_PROTOCOL          *This,\r
  IN  UINT32                         TimerIndex,\r
  OUT UINT64                         *TimerValue,\r
  OUT UINT64                         *TimerPeriod   OPTIONAL\r
  )\r
{\r
  return EFI_UNSUPPORTED;\r
}\r
\r
/**\r
  Callback function for idle events.\r
\r
  @param  Event                 Event whose notification function is being invoked.\r
  @param  Context               The pointer to the notification function's context,\r
                                which is implementation-dependent.\r
\r
**/\r
VOID\r
EFIAPI\r
IdleLoopEventCallback (\r
  IN EFI_EVENT                Event,\r
  IN VOID                     *Context\r
  )\r
{\r
  CpuSleep ();\r
}\r
\r
//\r
// Globals used to initialize the protocol\r
//\r
EFI_HANDLE            mCpuHandle = NULL;\r
EFI_CPU_ARCH_PROTOCOL mCpu = {\r
  CpuFlushCpuDataCache,\r
  CpuEnableInterrupt,\r
  CpuDisableInterrupt,\r
  CpuGetInterruptState,\r
  CpuInit,\r
  CpuRegisterInterruptHandler,\r
  CpuGetTimerValue,\r
  CpuSetMemoryAttributes,\r
  0,          // NumberOfTimers\r
  2048,       // DmaBufferAlignment\r
};\r
\r
STATIC\r
VOID\r
InitializeDma (\r
  IN OUT  EFI_CPU_ARCH_PROTOCOL   *CpuArchProtocol\r
  )\r
{\r
  CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();\r
}\r
\r
EFI_STATUS\r
CpuDxeInitialize (\r
  IN EFI_HANDLE         ImageHandle,\r
  IN EFI_SYSTEM_TABLE   *SystemTable\r
  )\r
{\r
  EFI_STATUS  Status;\r
  EFI_EVENT    IdleLoopEvent;\r
\r
  InitializeExceptions (&mCpu);\r
\r
  InitializeDma (&mCpu);\r
\r
  Status = gBS->InstallMultipleProtocolInterfaces (\r
                &mCpuHandle,\r
                &gEfiCpuArchProtocolGuid,           &mCpu,\r
                NULL\r
                );\r
\r
  //\r
  // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r
  // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r
  // after the protocol is installed\r
  //\r
  mIsFlushingGCD = TRUE;\r
  SyncCacheConfig (&mCpu);\r
  mIsFlushingGCD = FALSE;\r
\r
  // If the platform is a MPCore system then install the Configuration Table describing the\r
  // secondary core states\r
  if (ArmIsMpCore()) {\r
    PublishArmProcessorTable();\r
  }\r
\r
  //\r
  // Setup a callback for idle events\r
  //\r
  Status = gBS->CreateEventEx (\r
                  EVT_NOTIFY_SIGNAL,\r
                  TPL_NOTIFY,\r
                  IdleLoopEventCallback,\r
                  NULL,\r
                  &gIdleLoopEventGuid,\r
                  &IdleLoopEvent\r
                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
}\r