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1 | //\r | |
2 | // Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
3 | // \r | |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | #include <Library/PcdLib.h>\r | |
16 | #include <AutoGen.h>\r | |
17 | \r | |
18 | INCLUDE AsmMacroIoLib.inc\r | |
19 | \r | |
20 | EXPORT InitializeSMC\r | |
21 | \r | |
22 | PRESERVE8\r | |
23 | AREA ModuleInitializeSMC, CODE, READONLY\r | |
24 | \r | |
25 | // Static memory configuation definitions for SMC\r | |
26 | SmcDirectCmd EQU 0x10\r | |
27 | SmcSetCycles EQU 0x14\r | |
28 | SmcSetOpMode EQU 0x18\r | |
29 | \r | |
30 | // CS0 CS0-Interf0 NOR1 flash on the motherboard\r | |
31 | // CS1 CS1-Interf0 Reserved for the motherboard\r | |
32 | // CS2 CS2-Interf0 SRAM on the motherboard\r | |
33 | // CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r | |
34 | // CS4 CS0-Interf1 NOR2 flash on the motherboard\r | |
35 | // CS5 CS1-Interf1 memory-mapped peripherals\r | |
36 | // CS6 CS2-Interf1 memory-mapped peripherals\r | |
37 | // CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r | |
38 | \r | |
39 | // IN r1 SmcBase\r | |
40 | // IN r2 VideoSRamBase\r | |
41 | // NOTE: This code is been called before any stack has been setup. It means some registers\r | |
42 | // could be overwritten (case of 'r0')\r | |
43 | InitializeSMC\r | |
44 | //\r | |
45 | // Setup NOR1 (CS0-Interface0)\r | |
46 | //\r | |
47 | \r | |
48 | //Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r | |
49 | //Read cycle timeout = 0xA (0:3)\r | |
50 | //Write cycle timeout = 0x3(7:4)\r | |
51 | //OE Assertion Delay = 0x9(11:8)\r | |
52 | //WE Assertion delay = 0x3(15:12)\r | |
53 | //Page cycle timeout = 0x2(19:16) \r | |
54 | ldr r0, = 0x0002393A\r | |
55 | str r0, [r1, #SmcSetCycles]\r | |
56 | \r | |
57 | //Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r | |
58 | // 0x00000002 = MemoryWidth: 32bit\r | |
59 | // 0x00000028 = ReadMemoryBurstLength:continuous\r | |
60 | // 0x00000280 = WriteMemoryBurstLength:continuous\r | |
61 | // 0x00000800 = Set Address Valid\r | |
62 | ldr r0, = 0x00000AAA\r | |
63 | str r0, [r1, #SmcSetOpMode] \r | |
64 | \r | |
65 | //Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r | |
66 | // 0x00000000 = ChipSelect0-Interface 0\r | |
67 | // 0x00400000 = CmdTypes: UpdateRegs\r | |
68 | ldr r0, = 0x00400000\r | |
69 | str r0, [r1, #SmcDirectCmd] \r | |
70 | \r | |
71 | //\r | |
72 | // Setup SRAM (CS2-Interface0)\r | |
73 | //\r | |
74 | ldr r0, = 0x00027158\r | |
75 | str r0, [r1, #SmcSetCycles]\r | |
76 | \r | |
77 | // 0x00000002 = MemoryWidth: 32bit\r | |
78 | // 0x00000800 = Set Address Valid\r | |
79 | ldr r0, = 0x00000802\r | |
80 | str r0, [r1, #SmcSetOpMode]\r | |
81 | \r | |
82 | // 0x01000000 = ChipSelect2-Interface 0\r | |
83 | // 0x00400000 = CmdTypes: UpdateRegs\r | |
84 | ldr r0, = 0x01400000\r | |
85 | str r0, [r1, #SmcDirectCmd]\r | |
86 | \r | |
87 | //\r | |
88 | // USB/Eth/VRAM (CS3-Interface0)\r | |
89 | //\r | |
90 | ldr r0, = 0x000CD2AA\r | |
91 | str r0, [r1, #SmcSetCycles]\r | |
92 | \r | |
93 | // 0x00000002 = MemoryWidth: 32bit\r | |
94 | // 0x00000004 = Memory reads are synchronous\r | |
95 | // 0x00000040 = Memory writes are synchronous\r | |
96 | ldr r0, = 0x00000046\r | |
97 | str r0, [r1, #SmcSetOpMode] \r | |
98 | \r | |
99 | // 0x01800000 = ChipSelect3-Interface 0\r | |
100 | // 0x00400000 = CmdTypes: UpdateRegs\r | |
101 | ldr r0, = 0x01C00000\r | |
102 | str r0, [r1, #SmcDirectCmd] \r | |
103 | \r | |
104 | //\r | |
105 | // Setup NOR3 (CS0-Interface1)\r | |
106 | //\r | |
107 | ldr r0, = 0x0002393A\r | |
108 | str r0, [r1, #SmcSetCycles]\r | |
109 | \r | |
110 | // 0x00000002 = MemoryWidth: 32bit\r | |
111 | // 0x00000028 = ReadMemoryBurstLength:continuous\r | |
112 | // 0x00000280 = WriteMemoryBurstLength:continuous\r | |
113 | // 0x00000800 = Set Address Valid\r | |
114 | ldr r0, = 0x00000AAA\r | |
115 | str r0, [r1, #SmcSetOpMode] \r | |
116 | \r | |
117 | // 0x02000000 = ChipSelect0-Interface 1\r | |
118 | // 0x00400000 = CmdTypes: UpdateRegs\r | |
119 | ldr r0, = 0x02400000\r | |
120 | str r0, [r1, #SmcDirectCmd] \r | |
121 | \r | |
122 | //\r | |
123 | // Setup Peripherals (CS3-Interface1)\r | |
124 | //\r | |
125 | ldr r0, = 0x00025156\r | |
126 | str r0, [r1, #SmcSetCycles]\r | |
127 | \r | |
128 | // 0x00000002 = MemoryWidth: 32bit\r | |
129 | // 0x00000004 = Memory reads are synchronous\r | |
130 | // 0x00000040 = Memory writes are synchronous\r | |
131 | ldr r0, = 0x00000046\r | |
132 | str r0, [r1, #SmcSetOpMode] \r | |
133 | \r | |
134 | // 0x03800000 = ChipSelect3-Interface 1\r | |
135 | // 0x00400000 = CmdTypes: UpdateRegs\r | |
136 | ldr r0, = 0x03C00000\r | |
137 | str r0, [r1, #SmcDirectCmd] \r | |
138 | \r | |
139 | //\r | |
140 | // Setup VRAM (CS1-Interface0)\r | |
141 | //\r | |
142 | ldr r0, = 0x00049249\r | |
143 | str r0, [r1, #SmcSetCycles]\r | |
144 | \r | |
145 | // 0x00000002 = MemoryWidth: 32bit\r | |
146 | // 0x00000004 = Memory reads are synchronous\r | |
147 | // 0x00000040 = Memory writes are synchronous\r | |
148 | ldr r0, = 0x00000046\r | |
149 | str r0, [r1, #SmcSetOpMode] \r | |
150 | \r | |
151 | // 0x00800000 = ChipSelect1-Interface 0\r | |
152 | // 0x00400000 = CmdTypes: UpdateRegs\r | |
153 | ldr r0, = 0x00C00000\r | |
154 | str r0, [r1, #SmcDirectCmd] \r | |
155 | \r | |
156 | //\r | |
157 | // Page mode setup for VRAM\r | |
158 | //\r | |
159 | //read current state \r | |
160 | ldr r0, [r2, #0] \r | |
161 | ldr r0, [r2, #0] \r | |
162 | ldr r0, = 0x00000000\r | |
163 | str r0, [r2, #0] \r | |
164 | ldr r0, [r2, #0] \r | |
165 | \r | |
166 | //enable page mode \r | |
167 | ldr r0, [r2, #0] \r | |
168 | ldr r0, [r2, #0] \r | |
169 | ldr r0, = 0x00000000\r | |
170 | str r0, [r2, #0] \r | |
171 | ldr r0, = 0x00900090\r | |
172 | str r0, [r2, #0] \r | |
173 | \r | |
174 | //confirm page mode enabled\r | |
175 | ldr r0, [r2, #0] \r | |
176 | ldr r0, [r2, #0] \r | |
177 | ldr r0, = 0x00000000\r | |
178 | str r0, [r2, #0] \r | |
179 | ldr r0, [r2, #0] \r | |
180 | \r | |
181 | bx lr\r | |
182 | \r | |
183 | END\r |