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1 | /** @file\r | |
2 | \r | |
3 | Copyright (c) 2012 - 2021, Arm Limited. All rights reserved.<BR>\r | |
4 | \r | |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | \r | |
7 | **/\r | |
8 | \r | |
9 | #ifndef ARM_CORTEX_A5X_H_\r | |
10 | #define ARM_CORTEX_A5X_H_\r | |
11 | \r | |
12 | //\r | |
13 | // Cortex A5x feature bit definitions\r | |
14 | //\r | |
15 | #define A5X_FEATURE_SMP (1 << 6)\r | |
16 | \r | |
17 | //\r | |
18 | // Helper functions to access CPU Extended Control Register\r | |
19 | //\r | |
20 | UINT64\r | |
21 | EFIAPI\r | |
22 | ArmReadCpuExCr (\r | |
23 | VOID\r | |
24 | );\r | |
25 | \r | |
26 | VOID\r | |
27 | EFIAPI\r | |
28 | ArmWriteCpuExCr (\r | |
29 | IN UINT64 Val\r | |
30 | );\r | |
31 | \r | |
32 | VOID\r | |
33 | EFIAPI\r | |
34 | ArmSetCpuExCrBit (\r | |
35 | IN UINT64 Bits\r | |
36 | );\r | |
37 | \r | |
38 | VOID\r | |
39 | EFIAPI\r | |
40 | ArmUnsetCpuExCrBit (\r | |
41 | IN UINT64 Bits\r | |
42 | );\r | |
43 | \r | |
44 | #endif // ARM_CORTEX_A5X_H_\r |