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1 | #------------------------------------------------------------------------------\r | |
2 | #\r | |
3 | # Copyright (c) 2011, ARM. All rights reserved.<BR>\r | |
4 | #\r | |
5 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | #\r | |
7 | #------------------------------------------------------------------------------\r | |
8 | \r | |
9 | .text\r | |
10 | .align 2\r | |
11 | GCC_ASM_EXPORT(__aeabi_uidiv)\r | |
12 | GCC_ASM_EXPORT(__aeabi_uidivmod)\r | |
13 | GCC_ASM_EXPORT(__aeabi_idiv)\r | |
14 | GCC_ASM_EXPORT(__aeabi_idivmod)\r | |
15 | \r | |
16 | # AREA Math, CODE, READONLY\r | |
17 | \r | |
18 | #\r | |
19 | #UINT32\r | |
20 | #EFIAPI\r | |
21 | #__aeabi_uidivmode (\r | |
22 | # IN UINT32 Dividen\r | |
23 | # IN UINT32 Divisor\r | |
24 | # );\r | |
25 | #\r | |
26 | \r | |
27 | ASM_PFX(__aeabi_uidiv):\r | |
28 | ASM_PFX(__aeabi_uidivmod):\r | |
29 | rsbs r12, r1, r0, LSR #4\r | |
30 | mov r2, #0\r | |
31 | bcc ASM_PFX(__arm_div4)\r | |
32 | rsbs r12, r1, r0, LSR #8\r | |
33 | bcc ASM_PFX(__arm_div8)\r | |
34 | mov r3, #0\r | |
35 | b ASM_PFX(__arm_div_large)\r | |
36 | \r | |
37 | #\r | |
38 | #INT32\r | |
39 | #EFIAPI\r | |
40 | #__aeabi_idivmode (\r | |
41 | # IN INT32 Dividen\r | |
42 | # IN INT32 Divisor\r | |
43 | # );\r | |
44 | #\r | |
45 | ASM_PFX(__aeabi_idiv):\r | |
46 | ASM_PFX(__aeabi_idivmod):\r | |
47 | orrs r12, r0, r1\r | |
48 | bmi ASM_PFX(__arm_div_negative)\r | |
49 | rsbs r12, r1, r0, LSR #1\r | |
50 | mov r2, #0\r | |
51 | bcc ASM_PFX(__arm_div1)\r | |
52 | rsbs r12, r1, r0, LSR #4\r | |
53 | bcc ASM_PFX(__arm_div4)\r | |
54 | rsbs r12, r1, r0, LSR #8\r | |
55 | bcc ASM_PFX(__arm_div8)\r | |
56 | mov r3, #0\r | |
57 | b ASM_PFX(__arm_div_large)\r | |
58 | ASM_PFX(__arm_div8):\r | |
59 | rsbs r12, r1, r0, LSR #7\r | |
60 | subcs r0, r0, r1, LSL #7\r | |
61 | adc r2, r2, r2\r | |
62 | rsbs r12, r1, r0,LSR #6\r | |
63 | subcs r0, r0, r1, LSL #6\r | |
64 | adc r2, r2, r2\r | |
65 | rsbs r12, r1, r0, LSR #5\r | |
66 | subcs r0, r0, r1, LSL #5\r | |
67 | adc r2, r2, r2\r | |
68 | rsbs r12, r1, r0, LSR #4\r | |
69 | subcs r0, r0, r1, LSL #4\r | |
70 | adc r2, r2, r2\r | |
71 | ASM_PFX(__arm_div4):\r | |
72 | rsbs r12, r1, r0, LSR #3\r | |
73 | subcs r0, r0, r1, LSL #3\r | |
74 | adc r2, r2, r2\r | |
75 | rsbs r12, r1, r0, LSR #2\r | |
76 | subcs r0, r0, r1, LSL #2\r | |
77 | adcs r2, r2, r2\r | |
78 | rsbs r12, r1, r0, LSR #1\r | |
79 | subcs r0, r0, r1, LSL #1\r | |
80 | adc r2, r2, r2\r | |
81 | ASM_PFX(__arm_div1):\r | |
82 | subs r1, r0, r1\r | |
83 | movcc r1, r0\r | |
84 | adc r0, r2, r2\r | |
85 | bx r14\r | |
86 | ASM_PFX(__arm_div_negative):\r | |
87 | ands r2, r1, #0x80000000\r | |
88 | rsbmi r1, r1, #0\r | |
89 | eors r3, r2, r0, ASR #32\r | |
90 | rsbcs r0, r0, #0\r | |
91 | rsbs r12, r1, r0, LSR #4\r | |
92 | bcc label1\r | |
93 | rsbs r12, r1, r0, LSR #8\r | |
94 | bcc label2\r | |
95 | ASM_PFX(__arm_div_large):\r | |
96 | lsl r1, r1, #6\r | |
97 | rsbs r12, r1, r0, LSR #8\r | |
98 | orr r2, r2, #0xfc000000\r | |
99 | bcc label2\r | |
100 | lsl r1, r1, #6\r | |
101 | rsbs r12, r1, r0, LSR #8\r | |
102 | orr r2, r2, #0x3f00000\r | |
103 | bcc label2\r | |
104 | lsl r1, r1, #6\r | |
105 | rsbs r12, r1, r0, LSR #8\r | |
106 | orr r2, r2, #0xfc000\r | |
107 | orrcs r2, r2, #0x3f00\r | |
108 | lslcs r1, r1, #6\r | |
109 | rsbs r12, r1, #0\r | |
110 | bcs ASM_PFX(__aeabi_idiv0)\r | |
111 | label3:\r | |
112 | lsrcs r1, r1, #6\r | |
113 | label2:\r | |
114 | rsbs r12, r1, r0, LSR #7\r | |
115 | subcs r0, r0, r1, LSL #7\r | |
116 | adc r2, r2, r2\r | |
117 | rsbs r12, r1, r0, LSR #6\r | |
118 | subcs r0, r0, r1, LSL #6\r | |
119 | adc r2, r2, r2\r | |
120 | rsbs r12, r1, r0, LSR #5\r | |
121 | subcs r0, r0, r1, LSL #5\r | |
122 | adc r2, r2, r2\r | |
123 | rsbs r12, r1, r0, LSR #4\r | |
124 | subcs r0, r0, r1, LSL #4\r | |
125 | adc r2, r2, r2\r | |
126 | label1:\r | |
127 | rsbs r12, r1, r0, LSR #3\r | |
128 | subcs r0, r0, r1, LSL #3\r | |
129 | adc r2, r2, r2\r | |
130 | rsbs r12, r1, r0, LSR #2\r | |
131 | subcs r0, r0, r1, LSL #2\r | |
132 | adcs r2, r2, r2\r | |
133 | bcs label3\r | |
134 | rsbs r12, r1, r0, LSR #1\r | |
135 | subcs r0, r0, r1, LSL #1\r | |
136 | adc r2, r2, r2\r | |
137 | subs r1, r0, r1\r | |
138 | movcc r1, r0\r | |
139 | adc r0, r2, r2\r | |
140 | asrs r3, r3, #31\r | |
141 | rsbmi r0, r0, #0\r | |
142 | rsbcs r1, r1, #0\r | |
143 | bx r14\r | |
144 | \r | |
145 | @ What to do about division by zero? For now, just return.\r | |
146 | ASM_PFX(__aeabi_idiv0):\r | |
147 | bx r14\r |