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ArmVirtPkg/PrePi: base GCD memory space size on CPU's PA range
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1/** @file\r
2*\r
3* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
4*\r
5* This program and the accompanying materials\r
6* are licensed and made available under the terms and conditions of the BSD License\r
7* which accompanies this distribution. The full text of the license may be found at\r
8* http://opensource.org/licenses/bsd-license.php\r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12*\r
13**/\r
14\r
15#include <PiPei.h>\r
16#include <Pi/PiBootMode.h>\r
17\r
18#include <Library/PrePiLib.h>\r
19#include <Library/PrintLib.h>\r
20#include <Library/PrePiHobListPointerLib.h>\r
21#include <Library/TimerLib.h>\r
22#include <Library/PerformanceLib.h>\r
23#include <Library/CacheMaintenanceLib.h>\r
24\r
25#include <Ppi/GuidedSectionExtraction.h>\r
26#include <Ppi/ArmMpCoreInfo.h>\r
27\r
28#include "PrePi.h"\r
29\r
30VOID\r
31EFIAPI\r
32ProcessLibraryConstructorList (\r
33 VOID\r
34 );\r
35\r
36VOID\r
37PrePiMain (\r
38 IN UINTN UefiMemoryBase,\r
39 IN UINTN StacksBase,\r
40 IN UINT64 StartTimeStamp\r
41 )\r
42{\r
43 EFI_HOB_HANDOFF_INFO_TABLE* HobList;\r
44 EFI_STATUS Status;\r
45 CHAR8 Buffer[100];\r
46 UINTN CharCount;\r
47 UINTN StacksSize;\r
48\r
49 // Initialize the architecture specific bits\r
50 ArchInitialize ();\r
51\r
52 // Declare the PI/UEFI memory region\r
53 HobList = HobConstructor (\r
54 (VOID*)UefiMemoryBase,\r
55 FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),\r
56 (VOID*)UefiMemoryBase,\r
57 (VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks\r
58 );\r
59 PrePeiSetHobList (HobList);\r
60\r
61 //\r
62 // Ensure that the loaded image is invalidated in the caches, so that any\r
63 // modifications we made with the caches and MMU off (such as the applied\r
64 // relocations) don't become invisible once we turn them on.\r
65 //\r
66 InvalidateDataCacheRange((VOID *)(UINTN)PcdGet64 (PcdFdBaseAddress), PcdGet32 (PcdFdSize));\r
67\r
68 // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)\r
69 Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r
70 ASSERT_EFI_ERROR (Status);\r
71\r
72 // Initialize the Serial Port\r
73 SerialPortInitialize ();\r
74 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",\r
75 (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
76 SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
77\r
78 // Create the Stacks HOB (reserve the memory for all stacks)\r
79 StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);\r
80 BuildStackHob (StacksBase, StacksSize);\r
81\r
82 //TODO: Call CpuPei as a library\r
83 BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));\r
84\r
85 // Set the Boot Mode\r
86 SetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
87\r
88 // Initialize Platform HOBs (CpuHob and FvHob)\r
89 Status = PlatformPeim ();\r
90 ASSERT_EFI_ERROR (Status);\r
91\r
92 // Now, the HOB List has been initialized, we can register performance information\r
93 PERF_START (NULL, "PEI", NULL, StartTimeStamp);\r
94\r
95 // SEC phase needs to run library constructors by hand.\r
96 ProcessLibraryConstructorList ();\r
97\r
98 // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r
99 Status = DecompressFirstFv ();\r
100 ASSERT_EFI_ERROR (Status);\r
101\r
102 // Load the DXE Core and transfer control to it\r
103 Status = LoadDxeCoreFromFv (NULL, 0);\r
104 ASSERT_EFI_ERROR (Status);\r
105}\r
106\r
107VOID\r
108CEntryPoint (\r
109 IN UINTN MpId,\r
110 IN UINTN UefiMemoryBase,\r
111 IN UINTN StacksBase\r
112 )\r
113{\r
114 UINT64 StartTimeStamp;\r
115\r
116 if (PerformanceMeasurementEnabled ()) {\r
117 // Initialize the Timer Library to setup the Timer HW controller\r
118 TimerConstructor ();\r
119 // We cannot call yet the PerformanceLib because the HOB List has not been initialized\r
120 StartTimeStamp = GetPerformanceCounter ();\r
121 } else {\r
122 StartTimeStamp = 0;\r
123 }\r
124\r
125 // Data Cache enabled on Primary core when MMU is enabled.\r
126 ArmDisableDataCache ();\r
127 // Invalidate instruction cache\r
128 ArmInvalidateInstructionCache ();\r
129 // Enable Instruction Caches on all cores.\r
130 ArmEnableInstructionCache ();\r
131\r
132 PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r
133\r
134 // DXE Core should always load and never return\r
135 ASSERT (FALSE);\r
136}\r