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1 | /*++\r | |
2 | \r | |
3 | Copyright (c) 2006, Intel Corporation. All rights reserved. \r | |
4 | This software and associated documentation (if any) is furnished\r | |
5 | under a license and may only be used or copied in accordance\r | |
6 | with the terms of the license. Except as permitted by such\r | |
7 | license, no part of this software or documentation may be\r | |
8 | reproduced, stored in a retrieval system, or transmitted in any\r | |
9 | form or by any means without the express written consent of\r | |
10 | Intel Corporation.\r | |
11 | \r | |
12 | \r | |
13 | Module Name:\r | |
14 | \r | |
15 | fdc.h\r | |
16 | \r | |
17 | Abstract: \r | |
18 | \r | |
19 | \r | |
20 | Revision History\r | |
21 | --*/\r | |
22 | \r | |
23 | #ifndef _PEI_RECOVERY_FDC_H\r | |
24 | #define _PEI_RECOVERY_FDC_H\r | |
25 | \r | |
26 | //\r | |
27 | // FDC Registers\r | |
28 | //\r | |
29 | #define FDC_REGISTER_DOR 2 // 0x3F2 //Digital Output Register\r | |
30 | #define FDC_REGISTER_MSR 4 // 0x3F4 //Main Status Register\r | |
31 | #define FDC_REGISTER_DTR 5 // 0x3F5 //Data Register\r | |
32 | #define FDC_REGISTER_CCR 7 // 0x3F7 //Configuration Control Register(data rate select)\r | |
33 | #define FDC_REGISTER_DIR 7 // 0x3F7 //Digital Input Register(diskchange)\r | |
34 | //\r | |
35 | // FDC Register Bit Definitions\r | |
36 | //\r | |
37 | //\r | |
38 | // Digital Out Register(WO)\r | |
39 | //\r | |
40 | #define SELECT_DRV BIT0 // Select Drive: 0=A 1=B\r | |
41 | #define RESET_FDC BIT2 // Reset FDC\r | |
42 | #define INT_DMA_ENABLE BIT3 // Enable Int & DMA\r | |
43 | #define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor\r | |
44 | #define DRVB_MOTOR_ON BIT5 // Turn On Drive B Motor\r | |
45 | //\r | |
46 | // Main Status Register(RO)\r | |
47 | //\r | |
48 | #define MSR_DAB BIT0 // Drive A Busy\r | |
49 | #define MSR_DBB BIT1 // Drive B Busy\r | |
50 | #define MSR_CB BIT4 // FDC Busy\r | |
51 | #define MSR_NDM BIT5 // Non-DMA Mode\r | |
52 | #define MSR_DIO BIT6 // Data Input/Output\r | |
53 | #define MSR_RQM BIT7 // Request For Master\r | |
54 | //\r | |
55 | // Configuration Control Register(WO)\r | |
56 | //\r | |
57 | #define CCR_DRC (BIT0 | BIT1) // Data Rate select\r | |
58 | //\r | |
59 | // Digital Input Register(RO)\r | |
60 | //\r | |
61 | #define DIR_DCL BIT7 // Disk change line\r | |
62 | #define DRC_500KBS 0x0 // 500K\r | |
63 | #define DRC_300KBS 0x01 // 300K\r | |
64 | #define DRC_250KBS 0x02 // 250K\r | |
65 | //\r | |
66 | // FDC Command Code\r | |
67 | //\r | |
68 | #define READ_DATA_CMD 0x06\r | |
69 | #define SEEK_CMD 0x0F\r | |
70 | #define RECALIBRATE_CMD 0x07\r | |
71 | #define SENSE_INT_STATUS_CMD 0x08\r | |
72 | #define SPECIFY_CMD 0x03\r | |
73 | #define SENSE_DRV_STATUS_CMD 0x04\r | |
74 | \r | |
75 | //\r | |
76 | // CMD_MT: Multi_Track Selector\r | |
77 | // when set , this flag selects the multi-track operating mode.\r | |
78 | // In this mode, the FDC treats a complete cylinder under head0 and 1 as a single track\r | |
79 | //\r | |
80 | #define CMD_MT BIT7\r | |
81 | \r | |
82 | //\r | |
83 | // CMD_MFM: MFM/FM Mode Selector\r | |
84 | // A one selects the double density(MFM) mode\r | |
85 | // A zero selects single density (FM) mode\r | |
86 | //\r | |
87 | #define CMD_MFM BIT6\r | |
88 | \r | |
89 | //\r | |
90 | // CMD_SK: Skip Flag\r | |
91 | // When set to 1, sectors containing a deleted data address mark will automatically be skipped\r | |
92 | // during the execution of Read Data.\r | |
93 | // When set to 0, the sector is read or written the same as the read and write commands.\r | |
94 | //\r | |
95 | #define CMD_SK BIT5\r | |
96 | \r | |
97 | //\r | |
98 | // FDC Status Register Bit Definitions\r | |
99 | //\r | |
100 | //\r | |
101 | // Status Register 0\r | |
102 | //\r | |
103 | #define STS0_IC (BIT7 | BIT6) // Interrupt Code\r | |
104 | #define STS0_SE BIT5 // Seek End: the FDC completed a seek or recalibrate command\r | |
105 | #define STS0_EC BIT4 // Equipment Check\r | |
106 | #define STS0_NR BIT3 // Not Ready(unused), this bit is always 0\r | |
107 | #define STS0_HA BIT2 // Head Address: the current head address\r | |
108 | // STS0_US1 & STS0_US0: Drive Select(the current selected drive)\r | |
109 | //\r | |
110 | #define STS0_US1 BIT1 // Unit Select1\r | |
111 | #define STS0_US0 BIT0 // Unit Select0\r | |
112 | //\r | |
113 | // Status Register 1\r | |
114 | //\r | |
115 | #define STS1_EN BIT7 // End of Cylinder\r | |
116 | // BIT6 is unused\r | |
117 | //\r | |
118 | #define STS1_DE BIT5 // Data Error: The FDC detected a CRC error in either the ID field or data field of a sector\r | |
119 | #define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service within the required time interval\r | |
120 | // BIT3 is unused\r | |
121 | //\r | |
122 | #define STS1_ND BIT2 // No data\r | |
123 | #define STS1_NW BIT1 // Not Writable\r | |
124 | #define STS1_MA BIT0 // Missing Address Mark\r | |
125 | //\r | |
126 | // Status Register 2\r | |
127 | //\r | |
128 | // BIT7 is unused\r | |
129 | //\r | |
130 | #define STS2_CM BIT6 // Control Mark\r | |
131 | #define STS2_DD BIT5 // Data Error in Data Field: The FDC detected a CRC error in the data field\r | |
132 | #define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from the track address maintained inside FDC\r | |
133 | // #define STS2_SH BIT3 // Scan Equal Hit\r | |
134 | // #define STS2_SN BIT2 // Scan Not Satisfied\r | |
135 | // BIT3 is unused\r | |
136 | // BIT2 is unused\r | |
137 | //\r | |
138 | #define STS2_BC BIT1 // Bad Cylinder\r | |
139 | #define STS2_MD BIT0 // Missing Address Mark in DataField\r | |
140 | // Status Register 3\r | |
141 | // #define STS3_FT BIT7 // Fault\r | |
142 | // BIT7 is unused\r | |
143 | //\r | |
144 | #define STS3_WP BIT6 // Write Protected\r | |
145 | // #define STS3_RDY BIT5 // Ready\r | |
146 | // BIT5 is unused\r | |
147 | //\r | |
148 | #define STS3_T0 BIT4 // Track 0\r | |
149 | // #define STS3_TS BIT3 // Two Side\r | |
150 | // BIT3 is unused\r | |
151 | //\r | |
152 | #define STS3_HD BIT2 // Head Address\r | |
153 | // STS3_US1 & STS3_US0 : Drive Select\r | |
154 | //\r | |
155 | #define STS3_US1 BIT1 // Unit Select1\r | |
156 | #define STS3_US0 BIT0 // Unit Select0\r | |
157 | //\r | |
158 | // Status Register 0 Interrupt Code Description\r | |
159 | //\r | |
160 | #define IC_NT 0x0 // Normal Termination of Command\r | |
161 | #define IC_AT 0x40 // Abnormal Termination of Command\r | |
162 | #define IC_IC 0x80 // Invalid Command\r | |
163 | #define IC_ATRC 0xC0 // Abnormal Termination caused by Polling\r | |
164 | typedef struct {\r | |
165 | UINT8 EOT; // End of track\r | |
166 | UINT8 GPL; // Gap length\r | |
167 | UINT8 DTL; // Data length\r | |
168 | UINT8 Number; // Number of bytes per sector\r | |
169 | UINT8 MaxTrackNum;\r | |
170 | UINT8 MotorStartTime;\r | |
171 | UINT8 MotorOffTime;\r | |
172 | UINT8 HeadSettlingTime;\r | |
173 | UINT8 DataTransferRate;\r | |
174 | } DISKET_PARA_TABLE;\r | |
175 | \r | |
176 | typedef struct {\r | |
177 | UINT8 CommandCode;\r | |
178 | UINT8 DiskHeadSel;\r | |
179 | UINT8 Cylinder;\r | |
180 | UINT8 Head;\r | |
181 | UINT8 Sector;\r | |
182 | UINT8 Number;\r | |
183 | UINT8 EndOfTrack;\r | |
184 | UINT8 GapLength;\r | |
185 | UINT8 DataLength;\r | |
186 | } FDC_COMMAND_PACKET1;\r | |
187 | \r | |
188 | typedef struct {\r | |
189 | UINT8 CommandCode;\r | |
190 | UINT8 DiskHeadSel;\r | |
191 | } FDC_COMMAND_PACKET2;\r | |
192 | \r | |
193 | typedef struct {\r | |
194 | UINT8 CommandCode;\r | |
195 | UINT8 SrtHut;\r | |
196 | UINT8 HltNd;\r | |
197 | } FDC_SPECIFY_CMD;\r | |
198 | \r | |
199 | typedef struct {\r | |
200 | UINT8 CommandCode;\r | |
201 | UINT8 DiskHeadSel;\r | |
202 | UINT8 NewCylinder;\r | |
203 | } FDC_SEEK_CMD;\r | |
204 | \r | |
205 | typedef struct {\r | |
206 | UINT8 Status0;\r | |
207 | UINT8 Status1;\r | |
208 | UINT8 Status2;\r | |
209 | UINT8 C;\r | |
210 | UINT8 H;\r | |
211 | UINT8 S;\r | |
212 | UINT8 Number;\r | |
213 | } FDC_RESULT_PACKET;\r | |
214 | \r | |
215 | #endif\r |