| | 1 | /** @file\r |
| | 2 | Intel FSP API definition from Intel Firmware Support Package External\r |
| | 3 | Architecture Specification v2.0 - v2.2\r |
| | 4 | \r |
| | 5 | Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r |
| | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| | 7 | \r |
| | 8 | **/\r |
| | 9 | \r |
| | 10 | #ifndef _FSP_API_H_\r |
| | 11 | #define _FSP_API_H_\r |
| | 12 | \r |
| | 13 | #include <Pi/PiStatusCode.h>\r |
| | 14 | \r |
| | 15 | ///\r |
| | 16 | /// FSP Reset Status code\r |
| | 17 | /// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code\r |
| | 18 | /// @{\r |
| | 19 | #define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001\r |
| | 20 | #define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002\r |
| | 21 | #define FSP_STATUS_RESET_REQUIRED_3 0x40000003\r |
| | 22 | #define FSP_STATUS_RESET_REQUIRED_4 0x40000004\r |
| | 23 | #define FSP_STATUS_RESET_REQUIRED_5 0x40000005\r |
| | 24 | #define FSP_STATUS_RESET_REQUIRED_6 0x40000006\r |
| | 25 | #define FSP_STATUS_RESET_REQUIRED_7 0x40000007\r |
| | 26 | #define FSP_STATUS_RESET_REQUIRED_8 0x40000008\r |
| | 27 | /// @}\r |
| | 28 | \r |
| | 29 | ///\r |
| | 30 | /// FSP Event related definition.\r |
| | 31 | ///\r |
| | 32 | #define FSP_EVENT_CODE 0xF5000000\r |
| | 33 | #define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)\r |
| | 34 | \r |
| | 35 | /*\r |
| | 36 | FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues.\r |
| | 37 | These events fall under three catagories: Error, Progress, and Debug. The event reporting mechanism follows the\r |
| | 38 | status code services described in section 6 and 7 of the PI Specification v1.7 Volume 3.\r |
| | 39 | \r |
| | 40 | @param[in] Type Indicates the type of event being reported.\r |
| | 41 | See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_TYPE.\r |
| | 42 | @param[in] Value Describes the current status of a hardware or software entity.\r |
| | 43 | This includes information about the class and subclass that is used to classify the entity as well as an operation.\r |
| | 44 | For progress events, the operation is the current activity. For error events, it is the exception.\r |
| | 45 | For debug events, it is not defined at this time.\r |
| | 46 | See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_VALUE.\r |
| | 47 | @param[in] Instance The enumeration of a hardware or software entity within the system.\r |
| | 48 | A system may contain multiple entities that match a class/subclass pairing. The instance differentiates between them.\r |
| | 49 | An instance of 0 indicates that instance information is unavailable, not meaningful, or not relevant.\r |
| | 50 | Valid instance numbers start with 1.\r |
| | 51 | @param[in] *CallerId This parameter can be used to identify the sub-module within the FSP generating the event.\r |
| | 52 | This parameter may be NULL.\r |
| | 53 | @param[in] *Data This optional parameter may be used to pass additional data. The contents can have event-specific data.\r |
| | 54 | For example, the FSP provides a EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending debug messages.\r |
| | 55 | This parameter is NULL when no additional data is provided.\r |
| | 56 | \r |
| | 57 | @retval EFI_SUCCESS The event was handled successfully.\r |
| | 58 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r |
| | 59 | @retval EFI_DEVICE_ERROR The event handler failed.\r |
| | 60 | */\r |
| | 61 | typedef\r |
| | 62 | EFI_STATUS\r |
| | 63 | (EFIAPI *FSP_EVENT_HANDLER)(\r |
| | 64 | IN EFI_STATUS_CODE_TYPE Type,\r |
| | 65 | IN EFI_STATUS_CODE_VALUE Value,\r |
| | 66 | IN UINT32 Instance,\r |
| | 67 | IN OPTIONAL EFI_GUID *CallerId,\r |
| | 68 | IN OPTIONAL EFI_STATUS_CODE_DATA *Data\r |
| | 69 | );\r |
| | 70 | \r |
| | 71 | /*\r |
| | 72 | Handler for FSP-T debug log messages, provided by the bootloader.\r |
| | 73 | \r |
| | 74 | @param[in] DebugMessage A pointer to the debug message to be written to the log.\r |
| | 75 | @param[in] MessageLength Number of bytes to written to the debug log.\r |
| | 76 | \r |
| | 77 | @retval UINT32 The return value indicates the number of bytes actually written to\r |
| | 78 | the debug log. If the return value is less than MessageLength,\r |
| | 79 | an error occurred.\r |
| | 80 | */\r |
| | 81 | typedef\r |
| | 82 | UINT32\r |
| | 83 | (EFIAPI *FSP_DEBUG_HANDLER)(\r |
| | 84 | IN CHAR8 *DebugMessage,\r |
| | 85 | IN UINT32 MessageLength\r |
| | 86 | );\r |
| | 87 | \r |
| | 88 | #pragma pack(1)\r |
| | 89 | ///\r |
| | 90 | /// FSP_UPD_HEADER Configuration.\r |
| | 91 | ///\r |
| | 92 | typedef struct {\r |
| | 93 | ///\r |
| | 94 | /// UPD Region Signature. This signature will be\r |
| | 95 | /// "XXXXXX_T" for FSP-T\r |
| | 96 | /// "XXXXXX_M" for FSP-M\r |
| | 97 | /// "XXXXXX_S" for FSP-S\r |
| | 98 | /// Where XXXXXX is an unique signature\r |
| | 99 | ///\r |
| | 100 | UINT64 Signature;\r |
| | 101 | ///\r |
| | 102 | /// Revision of the Data structure.\r |
| | 103 | /// For FSP spec 2.0/2.1 value is 1.\r |
| | 104 | /// For FSP spec 2.2 value is 2.\r |
| | 105 | ///\r |
| | 106 | UINT8 Revision;\r |
| | 107 | UINT8 Reserved[23];\r |
| | 108 | } FSP_UPD_HEADER;\r |
| | 109 | \r |
| | 110 | ///\r |
| | 111 | /// FSPT_ARCH_UPD Configuration.\r |
| | 112 | ///\r |
| | 113 | typedef struct {\r |
| | 114 | ///\r |
| | 115 | /// Revision of the structure is 1 for this version of the specification.\r |
| | 116 | ///\r |
| | 117 | UINT8 Revision;\r |
| | 118 | UINT8 Reserved[3];\r |
| | 119 | ///\r |
| | 120 | /// Length of the structure in bytes. The current value for this field is 32.\r |
| | 121 | ///\r |
| | 122 | UINT32 Length;\r |
| | 123 | ///\r |
| | 124 | /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages\r |
| | 125 | /// occurring during FSP execution.\r |
| | 126 | ///\r |
| | 127 | FSP_DEBUG_HANDLER FspDebugHandler;\r |
| | 128 | UINT8 Reserved1[20];\r |
| | 129 | } FSPT_ARCH_UPD;\r |
| | 130 | \r |
| | 131 | ///\r |
| | 132 | /// FSPT_ARCH2_UPD Configuration.\r |
| | 133 | ///\r |
| | 134 | typedef struct {\r |
| | 135 | ///\r |
| | 136 | /// Revision of the structure is 2 for this version of the specification.\r |
| | 137 | ///\r |
| | 138 | UINT8 Revision;\r |
| | 139 | UINT8 Reserved[3];\r |
| | 140 | ///\r |
| | 141 | /// Length of the structure in bytes. The current value for this field is 32.\r |
| | 142 | ///\r |
| | 143 | UINT32 Length;\r |
| | 144 | ///\r |
| | 145 | /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages\r |
| | 146 | /// occurring during FSP execution.\r |
| | 147 | ///\r |
| | 148 | EFI_PHYSICAL_ADDRESS FspDebugHandler;\r |
| | 149 | UINT8 Reserved1[16];\r |
| | 150 | } FSPT_ARCH2_UPD;\r |
| | 151 | \r |
| | 152 | ///\r |
| | 153 | /// FSPM_ARCH_UPD Configuration.\r |
| | 154 | ///\r |
| | 155 | typedef struct {\r |
| | 156 | ///\r |
| | 157 | /// Revision of the structure. For FSP v2.0 value is 1.\r |
| | 158 | ///\r |
| | 159 | UINT8 Revision;\r |
| | 160 | UINT8 Reserved[3];\r |
| | 161 | ///\r |
| | 162 | /// Pointer to the non-volatile storage (NVS) data buffer.\r |
| | 163 | /// If it is NULL it indicates the NVS data is not available.\r |
| | 164 | ///\r |
| | 165 | VOID *NvsBufferPtr;\r |
| | 166 | ///\r |
| | 167 | /// Pointer to the temporary stack base address to be\r |
| | 168 | /// consumed inside FspMemoryInit() API.\r |
| | 169 | ///\r |
| | 170 | VOID *StackBase;\r |
| | 171 | ///\r |
| | 172 | /// Temporary stack size to be consumed inside\r |
| | 173 | /// FspMemoryInit() API.\r |
| | 174 | ///\r |
| | 175 | UINT32 StackSize;\r |
| | 176 | ///\r |
| | 177 | /// Size of memory to be reserved by FSP below "top\r |
| | 178 | /// of low usable memory" for bootloader usage.\r |
| | 179 | ///\r |
| | 180 | UINT32 BootLoaderTolumSize;\r |
| | 181 | ///\r |
| | 182 | /// Current boot mode.\r |
| | 183 | ///\r |
| | 184 | UINT32 BootMode;\r |
| | 185 | ///\r |
| | 186 | /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.\r |
| | 187 | /// This value is only valid if Revision is >= 2.\r |
| | 188 | ///\r |
| | 189 | FSP_EVENT_HANDLER *FspEventHandler;\r |
| | 190 | UINT8 Reserved1[4];\r |
| | 191 | } FSPM_ARCH_UPD;\r |
| | 192 | \r |
| | 193 | ///\r |
| | 194 | /// FSPM_ARCH2_UPD Configuration.\r |
| | 195 | ///\r |
| | 196 | typedef struct {\r |
| | 197 | ///\r |
| | 198 | /// Revision of the structure is 3 for this version of the specification.\r |
| | 199 | ///\r |
| | 200 | UINT8 Revision;\r |
| | 201 | UINT8 Reserved[3];\r |
| | 202 | ///\r |
| | 203 | /// Length of the structure in bytes. The current value for this field is 64.\r |
| | 204 | ///\r |
| | 205 | UINT32 Length;\r |
| | 206 | ///\r |
| | 207 | /// Pointer to the temporary stack base address to be\r |
| | 208 | /// consumed inside FspMemoryInit() API.\r |
| | 209 | ///\r |
| | 210 | EFI_PHYSICAL_ADDRESS StackBase;\r |
| | 211 | ///\r |
| | 212 | /// Temporary stack size to be consumed inside\r |
| | 213 | /// FspMemoryInit() API.\r |
| | 214 | ///\r |
| | 215 | UINT64 StackSize;\r |
| | 216 | ///\r |
| | 217 | /// Size of memory to be reserved by FSP below "top\r |
| | 218 | /// of low usable memory" for bootloader usage.\r |
| | 219 | ///\r |
| | 220 | UINT32 BootLoaderTolumSize;\r |
| | 221 | ///\r |
| | 222 | /// Current boot mode.\r |
| | 223 | ///\r |
| | 224 | UINT32 BootMode;\r |
| | 225 | ///\r |
| | 226 | /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.\r |
| | 227 | /// This value is only valid if Revision is >= 2.\r |
| | 228 | ///\r |
| | 229 | EFI_PHYSICAL_ADDRESS FspEventHandler;\r |
| | 230 | UINT8 Reserved1[24];\r |
| | 231 | } FSPM_ARCH2_UPD;\r |
| | 232 | \r |
| | 233 | ///\r |
| | 234 | /// FSPS_ARCH_UPD Configuration.\r |
| | 235 | ///\r |
| | 236 | typedef struct {\r |
| | 237 | ///\r |
| | 238 | /// Revision of the structure is 1 for this version of the specification.\r |
| | 239 | ///\r |
| | 240 | UINT8 Revision;\r |
| | 241 | UINT8 Reserved[3];\r |
| | 242 | ///\r |
| | 243 | /// Length of the structure in bytes. The current value for this field is 32.\r |
| | 244 | ///\r |
| | 245 | UINT32 Length;\r |
| | 246 | ///\r |
| | 247 | /// FspEventHandler Optional event handler for the bootloader to be informed of events\r |
| | 248 | /// occurring during FSP execution.\r |
| | 249 | ///\r |
| | 250 | FSP_EVENT_HANDLER FspEventHandler;\r |
| | 251 | ///\r |
| | 252 | /// A FSP binary may optionally implement multi-phase silicon initialization,\r |
| | 253 | /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER\r |
| | 254 | /// is non-zero.\r |
| | 255 | /// To enable multi-phase silicon initialization, the bootloader must set\r |
| | 256 | /// EnableMultiPhaseSiliconInit to a non-zero value.\r |
| | 257 | ///\r |
| | 258 | UINT8 EnableMultiPhaseSiliconInit;\r |
| | 259 | UINT8 Reserved1[19];\r |
| | 260 | } FSPS_ARCH_UPD;\r |
| | 261 | \r |
| | 262 | ///\r |
| | 263 | /// FSPS_ARCH2_UPD Configuration.\r |
| | 264 | ///\r |
| | 265 | typedef struct {\r |
| | 266 | ///\r |
| | 267 | /// Revision of the structure is 2 for this version of the specification.\r |
| | 268 | ///\r |
| | 269 | UINT8 Revision;\r |
| | 270 | UINT8 Reserved[3];\r |
| | 271 | ///\r |
| | 272 | /// Length of the structure in bytes. The current value for this field is 32.\r |
| | 273 | ///\r |
| | 274 | UINT32 Length;\r |
| | 275 | ///\r |
| | 276 | /// FspEventHandler Optional event handler for the bootloader to be informed of events\r |
| | 277 | /// occurring during FSP execution.\r |
| | 278 | ///\r |
| | 279 | EFI_PHYSICAL_ADDRESS FspEventHandler;\r |
| | 280 | UINT8 Reserved1[16];\r |
| | 281 | } FSPS_ARCH2_UPD;\r |
| | 282 | \r |
| | 283 | ///\r |
| | 284 | /// FSPT_UPD_COMMON Configuration.\r |
| | 285 | ///\r |
| | 286 | typedef struct {\r |
| | 287 | ///\r |
| | 288 | /// FSP_UPD_HEADER Configuration.\r |
| | 289 | ///\r |
| | 290 | FSP_UPD_HEADER FspUpdHeader;\r |
| | 291 | } FSPT_UPD_COMMON;\r |
| | 292 | \r |
| | 293 | ///\r |
| | 294 | /// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above.\r |
| | 295 | ///\r |
| | 296 | typedef struct {\r |
| | 297 | ///\r |
| | 298 | /// FSP_UPD_HEADER Configuration.\r |
| | 299 | ///\r |
| | 300 | FSP_UPD_HEADER FspUpdHeader;\r |
| | 301 | \r |
| | 302 | ///\r |
| | 303 | /// FSPT_ARCH_UPD Configuration.\r |
| | 304 | ///\r |
| | 305 | FSPT_ARCH_UPD FsptArchUpd;\r |
| | 306 | } FSPT_UPD_COMMON_FSP22;\r |
| | 307 | \r |
| | 308 | ///\r |
| | 309 | /// FSPT_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r |
| | 310 | ///\r |
| | 311 | typedef struct {\r |
| | 312 | ///\r |
| | 313 | /// FSP_UPD_HEADER Configuration.\r |
| | 314 | ///\r |
| | 315 | FSP_UPD_HEADER FspUpdHeader;\r |
| | 316 | \r |
| | 317 | ///\r |
| | 318 | /// FSPT_ARCH2_UPD Configuration.\r |
| | 319 | ///\r |
| | 320 | FSPT_ARCH2_UPD FsptArchUpd;\r |
| | 321 | } FSPT_UPD_COMMON_FSP24;\r |
| | 322 | \r |
| | 323 | ///\r |
| | 324 | /// FSPM_UPD_COMMON Configuration.\r |
| | 325 | ///\r |
| | 326 | typedef struct {\r |
| | 327 | ///\r |
| | 328 | /// FSP_UPD_HEADER Configuration.\r |
| | 329 | ///\r |
| | 330 | FSP_UPD_HEADER FspUpdHeader;\r |
| | 331 | ///\r |
| | 332 | /// FSPM_ARCH_UPD Configuration.\r |
| | 333 | ///\r |
| | 334 | FSPM_ARCH_UPD FspmArchUpd;\r |
| | 335 | } FSPM_UPD_COMMON;\r |
| | 336 | \r |
| | 337 | ///\r |
| | 338 | /// FSPM_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r |
| | 339 | ///\r |
| | 340 | typedef struct {\r |
| | 341 | ///\r |
| | 342 | /// FSP_UPD_HEADER Configuration.\r |
| | 343 | ///\r |
| | 344 | FSP_UPD_HEADER FspUpdHeader;\r |
| | 345 | ///\r |
| | 346 | /// FSPM_ARCH2_UPD Configuration.\r |
| | 347 | ///\r |
| | 348 | FSPM_ARCH2_UPD FspmArchUpd;\r |
| | 349 | } FSPM_UPD_COMMON_FSP24;\r |
| | 350 | \r |
| | 351 | ///\r |
| | 352 | /// FSPS_UPD_COMMON Configuration.\r |
| | 353 | ///\r |
| | 354 | typedef struct {\r |
| | 355 | ///\r |
| | 356 | /// FSP_UPD_HEADER Configuration.\r |
| | 357 | ///\r |
| | 358 | FSP_UPD_HEADER FspUpdHeader;\r |
| | 359 | } FSPS_UPD_COMMON;\r |
| | 360 | \r |
| | 361 | ///\r |
| | 362 | /// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above.\r |
| | 363 | ///\r |
| | 364 | typedef struct {\r |
| | 365 | ///\r |
| | 366 | /// FSP_UPD_HEADER Configuration.\r |
| | 367 | ///\r |
| | 368 | FSP_UPD_HEADER FspUpdHeader;\r |
| | 369 | \r |
| | 370 | ///\r |
| | 371 | /// FSPS_ARCH_UPD Configuration.\r |
| | 372 | ///\r |
| | 373 | FSPS_ARCH_UPD FspsArchUpd;\r |
| | 374 | } FSPS_UPD_COMMON_FSP22;\r |
| | 375 | \r |
| | 376 | ///\r |
| | 377 | /// FSPS_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r |
| | 378 | ///\r |
| | 379 | typedef struct {\r |
| | 380 | ///\r |
| | 381 | /// FSP_UPD_HEADER Configuration.\r |
| | 382 | ///\r |
| | 383 | FSP_UPD_HEADER FspUpdHeader;\r |
| | 384 | \r |
| | 385 | ///\r |
| | 386 | /// FSPS_ARCH2_UPD Configuration.\r |
| | 387 | ///\r |
| | 388 | FSPS_ARCH2_UPD FspsArchUpd;\r |
| | 389 | } FSPS_UPD_COMMON_FSP24;\r |
| | 390 | \r |
| | 391 | ///\r |
| | 392 | /// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE.\r |
| | 393 | ///\r |
| | 394 | typedef enum {\r |
| | 395 | ///\r |
| | 396 | /// This stage is notified when the bootloader completes the\r |
| | 397 | /// PCI enumeration and the resource allocation for the\r |
| | 398 | /// PCI devices is complete.\r |
| | 399 | ///\r |
| | 400 | EnumInitPhaseAfterPciEnumeration = 0x20,\r |
| | 401 | ///\r |
| | 402 | /// This stage is notified just before the bootloader hand-off\r |
| | 403 | /// to the OS loader.\r |
| | 404 | ///\r |
| | 405 | EnumInitPhaseReadyToBoot = 0x40,\r |
| | 406 | ///\r |
| | 407 | /// This stage is notified just before the firmware/Preboot\r |
| | 408 | /// environment transfers management of all system resources\r |
| | 409 | /// to the OS or next level execution environment.\r |
| | 410 | ///\r |
| | 411 | EnumInitPhaseEndOfFirmware = 0xF0\r |
| | 412 | } FSP_INIT_PHASE;\r |
| | 413 | \r |
| | 414 | ///\r |
| | 415 | /// Definition of NOTIFY_PHASE_PARAMS.\r |
| | 416 | ///\r |
| | 417 | typedef struct {\r |
| | 418 | ///\r |
| | 419 | /// Notification phase used for NotifyPhase API\r |
| | 420 | ///\r |
| | 421 | FSP_INIT_PHASE Phase;\r |
| | 422 | } NOTIFY_PHASE_PARAMS;\r |
| | 423 | \r |
| | 424 | ///\r |
| | 425 | /// Action definition for FspMultiPhaseSiInit API\r |
| | 426 | ///\r |
| | 427 | typedef enum {\r |
| | 428 | EnumMultiPhaseGetNumberOfPhases = 0x0,\r |
| | 429 | EnumMultiPhaseExecutePhase = 0x1\r |
| | 430 | } FSP_MULTI_PHASE_ACTION;\r |
| | 431 | \r |
| | 432 | ///\r |
| | 433 | /// Data structure returned by FSP when bootloader calling\r |
| | 434 | /// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases)\r |
| | 435 | ///\r |
| | 436 | typedef struct {\r |
| | 437 | UINT32 NumberOfPhases;\r |
| | 438 | UINT32 PhasesExecuted;\r |
| | 439 | } FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS;\r |
| | 440 | \r |
| | 441 | ///\r |
| | 442 | /// FspMultiPhaseSiInit function parameter.\r |
| | 443 | ///\r |
| | 444 | /// For action 0 (EnumMultiPhaseGetNumberOfPhases):\r |
| | 445 | /// - PhaseIndex must be 0.\r |
| | 446 | /// - MultiPhaseParamPtr should point to an instance of FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS.\r |
| | 447 | ///\r |
| | 448 | /// For action 1 (EnumMultiPhaseExecutePhase):\r |
| | 449 | /// - PhaseIndex will be the phase that will be executed by FSP.\r |
| | 450 | /// - MultiPhaseParamPtr shall be NULL.\r |
| | 451 | ///\r |
| | 452 | typedef struct {\r |
| | 453 | IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;\r |
| | 454 | IN UINT32 PhaseIndex;\r |
| | 455 | IN OUT VOID *MultiPhaseParamPtr;\r |
| | 456 | } FSP_MULTI_PHASE_PARAMS;\r |
| | 457 | \r |
| | 458 | #pragma pack()\r |
| | 459 | \r |
| | 460 | /**\r |
| | 461 | This FSP API is called soon after coming out of reset and before memory and stack is\r |
| | 462 | available. This FSP API will load the microcode update, enable code caching for the\r |
| | 463 | region specified by the boot loader and also setup a temporary stack to be used until\r |
| | 464 | main memory is initialized.\r |
| | 465 | \r |
| | 466 | A hardcoded stack can be set up with the following values, and the "esp" register\r |
| | 467 | initialized to point to this hardcoded stack.\r |
| | 468 | 1. The return address where the FSP will return control after setting up a temporary\r |
| | 469 | stack.\r |
| | 470 | 2. A pointer to the input parameter structure\r |
| | 471 | \r |
| | 472 | However, since the stack is in ROM and not writeable, this FSP API cannot be called\r |
| | 473 | using the "call" instruction, but needs to be jumped to.\r |
| | 474 | \r |
| | 475 | @param[in] FsptUpdDataPtr Pointer to the FSPT_UPD data structure.\r |
| | 476 | \r |
| | 477 | @retval EFI_SUCCESS Temporary RAM was initialized successfully.\r |
| | 478 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r |
| | 479 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r |
| | 480 | @retval EFI_DEVICE_ERROR Temp RAM initialization failed.\r |
| | 481 | \r |
| | 482 | If this function is successful, the FSP initializes the ECX and EDX registers to point to\r |
| | 483 | a temporary but writeable memory range available to the boot loader and returns with\r |
| | 484 | FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary\r |
| | 485 | memory range and EDX points to the end of the range. Boot loader is free to use the\r |
| | 486 | whole range described. Typically the boot loader can reload the ESP register to point\r |
| | 487 | to the end of this returned range so that it can be used as a standard stack.\r |
| | 488 | **/\r |
| | 489 | typedef\r |
| | 490 | EFI_STATUS\r |
| | 491 | (EFIAPI *FSP_TEMP_RAM_INIT)(\r |
| | 492 | IN VOID *FsptUpdDataPtr\r |
| | 493 | );\r |
| | 494 | \r |
| | 495 | /**\r |
| | 496 | This FSP API is used to notify the FSP about the different phases in the boot process.\r |
| | 497 | This allows the FSP to take appropriate actions as needed during different initialization\r |
| | 498 | phases. The phases will be platform dependent and will be documented with the FSP\r |
| | 499 | release. The current FSP supports two notify phases:\r |
| | 500 | Post PCI enumeration\r |
| | 501 | Ready To Boot\r |
| | 502 | \r |
| | 503 | @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS\r |
| | 504 | \r |
| | 505 | @retval EFI_SUCCESS The notification was handled successfully.\r |
| | 506 | @retval EFI_UNSUPPORTED The notification was not called in the proper order.\r |
| | 507 | @retval EFI_INVALID_PARAMETER The notification code is invalid.\r |
| | 508 | **/\r |
| | 509 | typedef\r |
| | 510 | EFI_STATUS\r |
| | 511 | (EFIAPI *FSP_NOTIFY_PHASE)(\r |
| | 512 | IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr\r |
| | 513 | );\r |
| | 514 | \r |
| | 515 | /**\r |
| | 516 | This FSP API is called after TempRamInit and initializes the memory.\r |
| | 517 | This FSP API accepts a pointer to a data structure that will be platform dependent\r |
| | 518 | and defined for each FSP binary. This will be documented in Integration guide with\r |
| | 519 | each FSP release.\r |
| | 520 | After FspMemInit completes its execution, it passes the pointer to the HobList and\r |
| | 521 | returns to the boot loader from where it was called. BootLoader is responsible to\r |
| | 522 | migrate its stack and data to Memory.\r |
| | 523 | FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r |
| | 524 | complete the silicon initialization and provides bootloader an opportunity to get\r |
| | 525 | control after system memory is available and before the temporary RAM is torn down.\r |
| | 526 | \r |
| | 527 | @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data structure.\r |
| | 528 | @param[out] HobListPtr Pointer to receive the address of the HOB list.\r |
| | 529 | \r |
| | 530 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r |
| | 531 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r |
| | 532 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r |
| | 533 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r |
| | 534 | @retval EFI_OUT_OF_RESOURCES Stack range requested by FSP is not met.\r |
| | 535 | @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status codes will not be returned during S3.\r |
| | 536 | **/\r |
| | 537 | typedef\r |
| | 538 | EFI_STATUS\r |
| | 539 | (EFIAPI *FSP_MEMORY_INIT)(\r |
| | 540 | IN VOID *FspmUpdDataPtr,\r |
| | 541 | OUT VOID **HobListPtr\r |
| | 542 | );\r |
| | 543 | \r |
| | 544 | /**\r |
| | 545 | This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary\r |
| | 546 | memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure\r |
| | 547 | that will be platform dependent and defined for each FSP binary. This will be\r |
| | 548 | documented in Integration Guide.\r |
| | 549 | FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r |
| | 550 | complete the silicon initialization and provides bootloader an opportunity to get\r |
| | 551 | control after system memory is available and before the temporary RAM is torn down.\r |
| | 552 | \r |
| | 553 | @param[in] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure.\r |
| | 554 | This structure is normally defined in the Integration Guide.\r |
| | 555 | And if it is not defined in the Integration Guide, pass NULL.\r |
| | 556 | \r |
| | 557 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r |
| | 558 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r |
| | 559 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r |
| | 560 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r |
| | 561 | **/\r |
| | 562 | typedef\r |
| | 563 | EFI_STATUS\r |
| | 564 | (EFIAPI *FSP_TEMP_RAM_EXIT)(\r |
| | 565 | IN VOID *TempRamExitParamPtr\r |
| | 566 | );\r |
| | 567 | \r |
| | 568 | /**\r |
| | 569 | This FSP API is called after TempRamExit API.\r |
| | 570 | FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the\r |
| | 571 | silicon initialization.\r |
| | 572 | \r |
| | 573 | @param[in] FspsUpdDataPtr Pointer to the FSPS_UPD data structure.\r |
| | 574 | If NULL, FSP will use the default parameters.\r |
| | 575 | \r |
| | 576 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r |
| | 577 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r |
| | 578 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r |
| | 579 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r |
| | 580 | @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r |
| | 581 | **/\r |
| | 582 | typedef\r |
| | 583 | EFI_STATUS\r |
| | 584 | (EFIAPI *FSP_SILICON_INIT)(\r |
| | 585 | IN VOID *FspsUpdDataPtr\r |
| | 586 | );\r |
| | 587 | \r |
| | 588 | /**\r |
| | 589 | This FSP API is expected to be called after FspSiliconInit but before FspNotifyPhase.\r |
| | 590 | This FSP API provides multi-phase silicon initialization; which brings greater modularity\r |
| | 591 | beyond the existing FspSiliconInit() API. Increased modularity is achieved by adding an\r |
| | 592 | extra API to FSP-S. This allows the bootloader to add board specific initialization steps\r |
| | 593 | throughout the SiliconInit flow as needed.\r |
| | 594 | \r |
| | 595 | @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNumberOfPhases:\r |
| | 596 | FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr will contain\r |
| | 597 | how many phases supported by FSP.\r |
| | 598 | For action - EnumMultiPhaseExecutePhase:\r |
| | 599 | FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr shall be NULL.\r |
| | 600 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r |
| | 601 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r |
| | 602 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r |
| | 603 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r |
| | 604 | @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r |
| | 605 | **/\r |
| | 606 | typedef\r |
| | 607 | EFI_STATUS\r |
| | 608 | (EFIAPI *FSP_MULTI_PHASE_SI_INIT)(\r |
| | 609 | IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr\r |
| | 610 | );\r |
| | 611 | \r |
| | 612 | #endif\r |
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