[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.h

/** @file\r
\r
  This file contains the definination for host controller register operation routines.\r
\r
Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EFI_EHCI_REG_H_\r
#define _EFI_EHCI_REG_H_\r
\r
//\r
// EHCI register offset\r
//\r
\r
//\r
// Capability register offset\r
//\r
#define EHC_CAPLENGTH_OFFSET  0      // Capability register length offset\r
#define EHC_HCSPARAMS_OFFSET  0x04   // Structural Parameters 04-07h\r
#define EHC_HCCPARAMS_OFFSET  0x08   // Capability parameters offset\r
\r
//\r
// Capability register bit definition\r
//\r
#define HCSP_NPORTS  0x0F            // Number of root hub port\r
#define HCSP_PPC     0x10            // Port Power Control\r
#define HCCP_64BIT   0x01            // 64-bit addressing capability\r
\r
//\r
// Operational register offset\r
//\r
#define EHC_USBCMD_OFFSET       0x0  // USB command register offset\r
#define EHC_USBSTS_OFFSET       0x04 // Statue register offset\r
#define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset\r
#define EHC_FRINDEX_OFFSET      0x0C // Frame index offset\r
#define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset\r
#define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset\r
#define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset\r
#define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset\r
#define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset\r
\r
#define EHC_FRAME_LEN  1024\r
\r
//\r
// Register bit definition\r
//\r
#define CONFIGFLAG_ROUTE_EHC  0x01   // Route port to EHC\r
\r
#define USBCMD_RUN            0x01     // Run/stop\r
#define USBCMD_RESET          0x02     // Start the host controller reset\r
#define USBCMD_ENABLE_PERIOD  0x10     // Enable periodic schedule\r
#define USBCMD_ENABLE_ASYNC   0x20     // Enable asynchronous schedule\r
#define USBCMD_IAAD           0x40     // Interrupt on async advance doorbell\r
\r
#define USBSTS_IAA             0x20    // Interrupt on async advance\r
#define USBSTS_PERIOD_ENABLED  0x4000  // Periodic schedule status\r
#define USBSTS_ASYNC_ENABLED   0x8000  // Asynchronous schedule status\r
#define USBSTS_HALT            0x1000  // Host controller halted\r
#define USBSTS_SYS_ERROR       0x10    // Host system error\r
#define USBSTS_INTACK_MASK     0x003F  // Mask for the interrupt ACK, the WC\r
                                       // (write clean) bits in USBSTS register\r
\r
#define PORTSC_CONN            0x01    // Current Connect Status\r
#define PORTSC_CONN_CHANGE     0x02    // Connect Status Change\r
#define PORTSC_ENABLED         0x04    // Port Enable / Disable\r
#define PORTSC_ENABLE_CHANGE   0x08    // Port Enable / Disable Change\r
#define PORTSC_OVERCUR         0x10    // Over current Active\r
#define PORTSC_OVERCUR_CHANGE  0x20    // Over current Change\r
#define PORSTSC_RESUME         0x40    // Force Port Resume\r
#define PORTSC_SUSPEND         0x80    // Port Suspend State\r
#define PORTSC_RESET           0x100   // Port Reset\r
#define PORTSC_LINESTATE_K     0x400   // Line Status K-state\r
#define PORTSC_LINESTATE_J     0x800   // Line Status J-state\r
#define PORTSC_POWER           0x1000  // Port Power\r
#define PORTSC_OWNER           0x2000  // Port Owner\r
#define PORTSC_CHANGE_MASK     0x2A    // Mask of the port change bits,\r
                                       // they are WC (write clean)\r
//\r
// PCI Configuration Registers\r
//\r
#define EHC_BAR_INDEX  0               // how many bytes away from USB_BASE to 0x10\r
\r
//\r
// Debug port capability id\r
//\r
#define EHC_DEBUG_PORT_CAP_ID  0x0A\r
\r
#define EHC_LINK_TERMINATED(Link)  (((Link) & 0x01) != 0)\r
\r
#define EHC_ADDR(High, QhHw32)   \\r
        ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r
\r
#define EHCI_IS_DATAIN(EndpointAddr)  EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT16    HwState;\r
  UINT16    UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Ehci Data and Ctrl Structures\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT8    ProgInterface;\r
  UINT8    SubClassCode;\r
  UINT8    BaseCode;\r
} USB_CLASSC;\r
#pragma pack()\r
\r
/**\r
  Read EHCI capability register.\r
\r
  @param  Ehc     The EHCI device.\r
  @param  Offset  Capability register address.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadCapRegister (\r
  IN  USB2_HC_DEV  *Ehc,\r
  IN  UINT32       Offset\r
  );\r
\r
/**\r
  Check whether the host controller has an in-use debug port.\r
\r
  @param[in] Ehc         The Enhanced Host Controller to query.\r
\r
  @param[in] PortNumber  If PortNumber is not NULL, then query whether\r
                         PortNumber is an in-use debug port on Ehc. (PortNumber\r
                         is taken in UEFI notation, i.e., zero-based.)\r
                         Otherwise, query whether Ehc has any in-use debug\r
                         port.\r
\r
  @retval TRUE   PortNumber is an in-use debug port on Ehc (if PortNumber is\r
                 not NULL), or some port on Ehc is an in-use debug port\r
                 (otherwise).\r
\r
  @retval FALSE  PortNumber is not an in-use debug port on Ehc (if PortNumber\r
                 is not NULL), or no port on Ehc is an in-use debug port\r
                 (otherwise).\r
**/\r
BOOLEAN\r
EhcIsDebugPortInUse (\r
  IN CONST USB2_HC_DEV  *Ehc,\r
  IN CONST UINT8        *PortNumber OPTIONAL\r
  );\r
\r
/**\r
  Read EHCI Operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   The operation register offset.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadOpReg (\r
  IN  USB2_HC_DEV  *Ehc,\r
  IN  UINT32       Offset\r
  );\r
\r
/**\r
  Write  the data to the EHCI operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   EHCI operation register offset.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
EhcWriteOpReg (\r
  IN USB2_HC_DEV  *Ehc,\r
  IN UINT32       Offset,\r
  IN UINT32       Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
EhcSetOpRegBit (\r
  IN USB2_HC_DEV  *Ehc,\r
  IN UINT32       Offset,\r
  IN UINT32       Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
EhcClearOpRegBit (\r
  IN USB2_HC_DEV  *Ehc,\r
  IN UINT32       Offset,\r
  IN UINT32       Bit\r
  );\r
\r
/**\r
  Add support for UEFI Over Legacy (UoL) feature, stop\r
  the legacy USB SMI support.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcClearLegacySupport (\r
  IN USB2_HC_DEV  *Ehc\r
  );\r
\r
/**\r
  Set door bell and wait it to be ACKed by host controller.\r
  This function is used to synchronize with the hardware.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  Synchronized with the hardware.\r
  @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.\r
\r
**/\r
EFI_STATUS\r
EhcSetAndWaitDoorBell (\r
  IN  USB2_HC_DEV  *Ehc,\r
  IN  UINT32       Timeout\r
  );\r
\r
/**\r
  Clear all the interrutp status bits, these bits are Write-Clean.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcAckAllInterrupt (\r
  IN  USB2_HC_DEV  *Ehc\r
  );\r
\r
/**\r
  Whether Ehc is halted.\r
\r
  @param  Ehc     The EHCI device.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
EhcIsHalt (\r
  IN USB2_HC_DEV  *Ehc\r
  );\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Ehc      The EHCI device.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
EhcIsSysError (\r
  IN USB2_HC_DEV  *Ehc\r
  );\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The host controller is reset.\r
  @return Others       Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
EhcResetHC (\r
  IN USB2_HC_DEV  *Ehc,\r
  IN UINT32       Timeout\r
  );\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is halt.\r
  @return EFI_TIMEOUT  Failed to halt the controller before Timeout.\r
\r
**/\r
EFI_STATUS\r
EhcHaltHC (\r
  IN USB2_HC_DEV  *Ehc,\r
  IN UINT32       Timeout\r
  );\r
\r
/**\r
  Set the EHCI to run.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is running.\r
  @return Others       Failed to set the EHCI to run.\r
\r
**/\r
EFI_STATUS\r
EhcRunHC (\r
  IN USB2_HC_DEV  *Ehc,\r
  IN UINT32       Timeout\r
  );\r
\r
/**\r
  Initialize the HC hardware.\r
  EHCI spec lists the five things to do to initialize the hardware:\r
  1. Program CTRLDSSEGMENT\r
  2. Set USBINTR to enable interrupts\r
  3. Set periodic list base\r
  4. Set USBCMD, interrupt threshold, frame list size etc\r
  5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return EFI_SUCCESS  The EHCI has come out of halt state.\r
  @return EFI_TIMEOUT  Time out happened.\r
\r
**/\r
EFI_STATUS\r
EhcInitHC (\r
  IN USB2_HC_DEV  *Ehc\r
  );\r
\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	\r
	3	This file contains the definination for host controller register operation routines.\r
	4	\r
	5	Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r
	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
	7	\r
	8	**/\r
	9	\r
	10	#ifndef _EFI_EHCI_REG_H_\r
	11	#define _EFI_EHCI_REG_H_\r
	12	\r
	13	//\r
	14	// EHCI register offset\r
	15	//\r
	16	\r
	17	//\r
	18	// Capability register offset\r
	19	//\r
	20	#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r
	21	#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r
	22	#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r
	23	\r
	24	//\r
	25	// Capability register bit definition\r
	26	//\r
	27	#define HCSP_NPORTS 0x0F // Number of root hub port\r
	28	#define HCSP_PPC 0x10 // Port Power Control\r
	29	#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
	30	\r
	31	//\r
	32	// Operational register offset\r
	33	//\r
	34	#define EHC_USBCMD_OFFSET 0x0 // USB command register offset\r
	35	#define EHC_USBSTS_OFFSET 0x04 // Statue register offset\r
	36	#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset\r
	37	#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset\r
	38	#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset\r
	39	#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset\r
	40	#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset\r
	41	#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r
	42	#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r
	43	\r
	44	#define EHC_FRAME_LEN 1024\r
	45	\r
	46	//\r
	47	// Register bit definition\r
	48	//\r
	49	#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r
	50	\r
	51	#define USBCMD_RUN 0x01 // Run/stop\r
	52	#define USBCMD_RESET 0x02 // Start the host controller reset\r
	53	#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r
	54	#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r
	55	#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r
	56	\r
	57	#define USBSTS_IAA 0x20 // Interrupt on async advance\r
	58	#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r
	59	#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r
	60	#define USBSTS_HALT 0x1000 // Host controller halted\r
	61	#define USBSTS_SYS_ERROR 0x10 // Host system error\r
	62	#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r
	63	// (write clean) bits in USBSTS register\r
	64	\r
	65	#define PORTSC_CONN 0x01 // Current Connect Status\r
	66	#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r
	67	#define PORTSC_ENABLED 0x04 // Port Enable / Disable\r
	68	#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r
	69	#define PORTSC_OVERCUR 0x10 // Over current Active\r
	70	#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r
	71	#define PORSTSC_RESUME 0x40 // Force Port Resume\r
	72	#define PORTSC_SUSPEND 0x80 // Port Suspend State\r
	73	#define PORTSC_RESET 0x100 // Port Reset\r
	74	#define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r
	75	#define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r
	76	#define PORTSC_POWER 0x1000 // Port Power\r
	77	#define PORTSC_OWNER 0x2000 // Port Owner\r
	78	#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r
	79	// they are WC (write clean)\r
	80	//\r
	81	// PCI Configuration Registers\r
	82	//\r
	83	#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r
	84	\r
	85	//\r
	86	// Debug port capability id\r
	87	//\r
	88	#define EHC_DEBUG_PORT_CAP_ID 0x0A\r
	89	\r
	90	#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
	91	\r
	92	#define EHC_ADDR(High, QhHw32) \\r
	93	((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))\r
	94	\r
	95	#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
	96	\r
	97	//\r
	98	// Structure to map the hardware port states to the\r
	99	// UEFI's port states.\r
	100	//\r
	101	typedef struct {\r
	102	UINT16 HwState;\r
	103	UINT16 UefiState;\r
	104	} USB_PORT_STATE_MAP;\r
	105	\r
	106	//\r
	107	// Ehci Data and Ctrl Structures\r
	108	//\r
	109	#pragma pack(1)\r
	110	typedef struct {\r
	111	UINT8 ProgInterface;\r
	112	UINT8 SubClassCode;\r
	113	UINT8 BaseCode;\r
	114	} USB_CLASSC;\r
	115	#pragma pack()\r
	116	\r
	117	/**\r
	118	Read EHCI capability register.\r
	119	\r
	120	@param Ehc The EHCI device.\r
	121	@param Offset Capability register address.\r
	122	\r
	123	@return The register content.\r
	124	\r
	125	**/\r
	126	UINT32\r
	127	EhcReadCapRegister (\r
	128	IN USB2_HC_DEV *Ehc,\r
	129	IN UINT32 Offset\r
	130	);\r
	131	\r
	132	/**\r
	133	Check whether the host controller has an in-use debug port.\r
	134	\r
	135	@param[in] Ehc The Enhanced Host Controller to query.\r
	136	\r
	137	@param[in] PortNumber If PortNumber is not NULL, then query whether\r
	138	PortNumber is an in-use debug port on Ehc. (PortNumber\r
	139	is taken in UEFI notation, i.e., zero-based.)\r
	140	Otherwise, query whether Ehc has any in-use debug\r
	141	port.\r
	142	\r
	143	@retval TRUE PortNumber is an in-use debug port on Ehc (if PortNumber is\r
	144	not NULL), or some port on Ehc is an in-use debug port\r
	145	(otherwise).\r
	146	\r
	147	@retval FALSE PortNumber is not an in-use debug port on Ehc (if PortNumber\r
	148	is not NULL), or no port on Ehc is an in-use debug port\r
	149	(otherwise).\r
	150	**/\r
	151	BOOLEAN\r
	152	EhcIsDebugPortInUse (\r
	153	IN CONST USB2_HC_DEV *Ehc,\r
	154	IN CONST UINT8 *PortNumber OPTIONAL\r
	155	);\r
	156	\r
	157	/**\r
	158	Read EHCI Operation register.\r
	159	\r
	160	@param Ehc The EHCI device.\r
	161	@param Offset The operation register offset.\r
	162	\r
	163	@return The register content.\r
	164	\r
	165	**/\r
	166	UINT32\r
	167	EhcReadOpReg (\r
	168	IN USB2_HC_DEV *Ehc,\r
	169	IN UINT32 Offset\r
	170	);\r
	171	\r
	172	/**\r
	173	Write the data to the EHCI operation register.\r
	174	\r
	175	@param Ehc The EHCI device.\r
	176	@param Offset EHCI operation register offset.\r
	177	@param Data The data to write.\r
	178	\r
	179	**/\r
	180	VOID\r
	181	EhcWriteOpReg (\r
	182	IN USB2_HC_DEV *Ehc,\r
	183	IN UINT32 Offset,\r
	184	IN UINT32 Data\r
	185	);\r
	186	\r
	187	/**\r
	188	Set one bit of the operational register while keeping other bits.\r
	189	\r
	190	@param Ehc The EHCI device.\r
	191	@param Offset The offset of the operational register.\r
	192	@param Bit The bit mask of the register to set.\r
	193	\r
	194	**/\r
	195	VOID\r
	196	EhcSetOpRegBit (\r
	197	IN USB2_HC_DEV *Ehc,\r
	198	IN UINT32 Offset,\r
	199	IN UINT32 Bit\r
	200	);\r
	201	\r
	202	/**\r
	203	Clear one bit of the operational register while keeping other bits.\r
	204	\r
	205	@param Ehc The EHCI device.\r
	206	@param Offset The offset of the operational register.\r
	207	@param Bit The bit mask of the register to clear.\r
	208	\r
	209	**/\r
	210	VOID\r
	211	EhcClearOpRegBit (\r
	212	IN USB2_HC_DEV *Ehc,\r
	213	IN UINT32 Offset,\r
	214	IN UINT32 Bit\r
	215	);\r
	216	\r
	217	/**\r
	218	Add support for UEFI Over Legacy (UoL) feature, stop\r
	219	the legacy USB SMI support.\r
	220	\r
	221	@param Ehc The EHCI device.\r
	222	\r
	223	**/\r
	224	VOID\r
	225	EhcClearLegacySupport (\r
	226	IN USB2_HC_DEV *Ehc\r
	227	);\r
	228	\r
	229	/**\r
	230	Set door bell and wait it to be ACKed by host controller.\r
	231	This function is used to synchronize with the hardware.\r
	232	\r
	233	@param Ehc The EHCI device.\r
	234	@param Timeout The time to wait before abort (in millisecond, ms).\r
	235	\r
	236	@retval EFI_SUCCESS Synchronized with the hardware.\r
	237	@retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r
	238	\r
	239	**/\r
	240	EFI_STATUS\r
	241	EhcSetAndWaitDoorBell (\r
	242	IN USB2_HC_DEV *Ehc,\r
	243	IN UINT32 Timeout\r
	244	);\r
	245	\r
	246	/**\r
	247	Clear all the interrutp status bits, these bits are Write-Clean.\r
	248	\r
	249	@param Ehc The EHCI device.\r
	250	\r
	251	**/\r
	252	VOID\r
	253	EhcAckAllInterrupt (\r
	254	IN USB2_HC_DEV *Ehc\r
	255	);\r
	256	\r
	257	/**\r
	258	Whether Ehc is halted.\r
	259	\r
	260	@param Ehc The EHCI device.\r
	261	\r
	262	@retval TRUE The controller is halted.\r
	263	@retval FALSE It isn't halted.\r
	264	\r
	265	**/\r
	266	BOOLEAN\r
	267	EhcIsHalt (\r
	268	IN USB2_HC_DEV *Ehc\r
	269	);\r
	270	\r
	271	/**\r
	272	Whether system error occurred.\r
	273	\r
	274	@param Ehc The EHCI device.\r
	275	\r
	276	@retval TRUE System error happened.\r
	277	@retval FALSE No system error.\r
	278	\r
	279	**/\r
	280	BOOLEAN\r
	281	EhcIsSysError (\r
	282	IN USB2_HC_DEV *Ehc\r
	283	);\r
	284	\r
	285	/**\r
	286	Reset the host controller.\r
	287	\r
	288	@param Ehc The EHCI device.\r
	289	@param Timeout Time to wait before abort (in millisecond, ms).\r
	290	\r
	291	@retval EFI_SUCCESS The host controller is reset.\r
	292	@return Others Failed to reset the host.\r
	293	\r
	294	**/\r
	295	EFI_STATUS\r
	296	EhcResetHC (\r
	297	IN USB2_HC_DEV *Ehc,\r
	298	IN UINT32 Timeout\r
	299	);\r
	300	\r
	301	/**\r
	302	Halt the host controller.\r
	303	\r
	304	@param Ehc The EHCI device.\r
	305	@param Timeout Time to wait before abort.\r
	306	\r
	307	@return EFI_SUCCESS The EHCI is halt.\r
	308	@return EFI_TIMEOUT Failed to halt the controller before Timeout.\r
	309	\r
	310	**/\r
	311	EFI_STATUS\r
	312	EhcHaltHC (\r
	313	IN USB2_HC_DEV *Ehc,\r
	314	IN UINT32 Timeout\r
	315	);\r
	316	\r
	317	/**\r
	318	Set the EHCI to run.\r
	319	\r
	320	@param Ehc The EHCI device.\r
	321	@param Timeout Time to wait before abort.\r
	322	\r
	323	@return EFI_SUCCESS The EHCI is running.\r
	324	@return Others Failed to set the EHCI to run.\r
	325	\r
	326	**/\r
	327	EFI_STATUS\r
	328	EhcRunHC (\r
	329	IN USB2_HC_DEV *Ehc,\r
	330	IN UINT32 Timeout\r
	331	);\r
	332	\r
	333	/**\r
	334	Initialize the HC hardware.\r
	335	EHCI spec lists the five things to do to initialize the hardware:\r
	336	1. Program CTRLDSSEGMENT\r
	337	2. Set USBINTR to enable interrupts\r
	338	3. Set periodic list base\r
	339	4. Set USBCMD, interrupt threshold, frame list size etc\r
	340	5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
	341	\r
	342	@param Ehc The EHCI device.\r
	343	\r
	344	@return EFI_SUCCESS The EHCI has come out of halt state.\r
	345	@return EFI_TIMEOUT Time out happened.\r
	346	\r
	347	**/\r
	348	EFI_STATUS\r
	349	EhcInitHC (\r
	350	IN USB2_HC_DEV *Ehc\r
	351	);\r
	352	\r
	353	#endif\r