[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.h

/** @file\r
\r
  This file contains the definination for host controller register operation routines.\r
\r
Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_EHCI_REG_H_\r
#define _EFI_EHCI_REG_H_\r
\r
//\r
// EHCI register offset\r
//\r
\r
\r
//\r
// Capability register offset\r
//\r
#define EHC_CAPLENGTH_OFFSET    0    // Capability register length offset\r
#define EHC_HCSPARAMS_OFFSET    0x04 // Structural Parameters 04-07h\r
#define EHC_HCCPARAMS_OFFSET    0x08 // Capability parameters offset\r
\r
//\r
// Capability register bit definition\r
//\r
#define HCSP_NPORTS             0x0F // Number of root hub port\r
#define HCSP_PPC                0x10 // Port Power Control\r
#define HCCP_64BIT              0x01 // 64-bit addressing capability\r
\r
//\r
// Operational register offset\r
//\r
#define EHC_USBCMD_OFFSET       0x0  // USB command register offset\r
#define EHC_USBSTS_OFFSET       0x04 // Statue register offset\r
#define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset\r
#define EHC_FRINDEX_OFFSET      0x0C // Frame index offset\r
#define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset\r
#define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset\r
#define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset\r
#define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset\r
#define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset\r
\r
#define EHC_FRAME_LEN           1024\r
\r
//\r
// Register bit definition\r
//\r
#define CONFIGFLAG_ROUTE_EHC    0x01 // Route port to EHC\r
\r
#define USBCMD_RUN              0x01   // Run/stop\r
#define USBCMD_RESET            0x02   // Start the host controller reset\r
#define USBCMD_ENABLE_PERIOD    0x10   // Enable periodic schedule\r
#define USBCMD_ENABLE_ASYNC     0x20   // Enable asynchronous schedule\r
#define USBCMD_IAAD             0x40   // Interrupt on async advance doorbell\r
\r
#define USBSTS_IAA              0x20   // Interrupt on async advance\r
#define USBSTS_PERIOD_ENABLED   0x4000 // Periodic schedule status\r
#define USBSTS_ASYNC_ENABLED    0x8000 // Asynchronous schedule status\r
#define USBSTS_HALT             0x1000 // Host controller halted\r
#define USBSTS_SYS_ERROR        0x10   // Host system error\r
#define USBSTS_INTACK_MASK      0x003F // Mask for the interrupt ACK, the WC\r
                                       // (write clean) bits in USBSTS register\r
\r
#define PORTSC_CONN             0x01   // Current Connect Status\r
#define PORTSC_CONN_CHANGE      0x02   // Connect Status Change\r
#define PORTSC_ENABLED          0x04   // Port Enable / Disable\r
#define PORTSC_ENABLE_CHANGE    0x08   // Port Enable / Disable Change\r
#define PORTSC_OVERCUR          0x10   // Over current Active\r
#define PORTSC_OVERCUR_CHANGE   0x20   // Over current Change\r
#define PORSTSC_RESUME          0x40   // Force Port Resume\r
#define PORTSC_SUSPEND          0x80   // Port Suspend State\r
#define PORTSC_RESET            0x100  // Port Reset\r
#define PORTSC_LINESTATE_K      0x400  // Line Status K-state\r
#define PORTSC_LINESTATE_J      0x800  // Line Status J-state\r
#define PORTSC_POWER            0x1000 // Port Power\r
#define PORTSC_OWNER            0x2000 // Port Owner\r
#define PORTSC_CHANGE_MASK      0x2A   // Mask of the port change bits,\r
                                       // they are WC (write clean)\r
//\r
// PCI Configuration Registers\r
//\r
#define EHC_BAR_INDEX           0      // how many bytes away from USB_BASE to 0x10\r
\r
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
\r
#define EHC_ADDR(High, QhHw32)   \\r
        ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r
\r
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT16                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Ehci Data and Ctrl Structures\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT8                   ProgInterface;\r
  UINT8                   SubClassCode;\r
  UINT8                   BaseCode;\r
} USB_CLASSC;\r
#pragma pack()\r
\r
/**\r
  Read EHCI capability register.\r
\r
  @param  Ehc     The EHCI device.\r
  @param  Offset  Capability register address.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadCapRegister (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
\r
/**\r
  Read EHCI Operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   The operation register offset.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadOpReg (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
\r
/**\r
  Write  the data to the EHCI operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   EHCI operation register offset.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
EhcWriteOpReg (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
EhcSetOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
EhcClearOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Add support for UEFI Over Legacy (UoL) feature, stop\r
  the legacy USB SMI support.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcClearLegacySupport (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
\r
/**\r
  Set door bell and wait it to be ACKed by host controller.\r
  This function is used to synchronize with the hardware.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  Synchronized with the hardware.\r
  @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.\r
\r
**/\r
EFI_STATUS\r
EhcSetAndWaitDoorBell (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Clear all the interrutp status bits, these bits are Write-Clean.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcAckAllInterrupt (\r
  IN  USB2_HC_DEV         *Ehc\r
  );\r
\r
\r
\r
/**\r
  Whether Ehc is halted.\r
\r
  @param  Ehc     The EHCI device.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
EhcIsHalt (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Ehc      The EHCI device.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
EhcIsSysError (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The host controller is reset.\r
  @return Others       Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
EhcResetHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is halt.\r
  @return EFI_TIMEOUT  Failed to halt the controller before Timeout.\r
\r
**/\r
EFI_STATUS\r
EhcHaltHC (\r
  IN USB2_HC_DEV         *Ehc,\r
  IN UINT32              Timeout\r
  );\r
\r
\r
/**\r
  Set the EHCI to run.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is running.\r
  @return Others       Failed to set the EHCI to run.\r
\r
**/\r
EFI_STATUS\r
EhcRunHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
\r
/**\r
  Initialize the HC hardware.\r
  EHCI spec lists the five things to do to initialize the hardware:\r
  1. Program CTRLDSSEGMENT\r
  2. Set USBINTR to enable interrupts\r
  3. Set periodic list base\r
  4. Set USBCMD, interrupt threshold, frame list size etc\r
  5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return EFI_SUCCESS  The EHCI has come out of halt state.\r
  @return EFI_TIMEOUT  Time out happened.\r
\r
**/\r
EFI_STATUS\r
EhcInitHC (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	\r
	3	This file contains the definination for host controller register operation routines.\r
	4	\r
	5	Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef _EFI_EHCI_REG_H_\r
	17	#define _EFI_EHCI_REG_H_\r
	18	\r
	19	//\r
	20	// EHCI register offset\r
	21	//\r
	22	\r
	23	\r
	24	//\r
	25	// Capability register offset\r
	26	//\r
	27	#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r
	28	#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r
	29	#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r
	30	\r
	31	//\r
	32	// Capability register bit definition\r
	33	//\r
	34	#define HCSP_NPORTS 0x0F // Number of root hub port\r
	35	#define HCSP_PPC 0x10 // Port Power Control\r
	36	#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
	37	\r
	38	//\r
	39	// Operational register offset\r
	40	//\r
	41	#define EHC_USBCMD_OFFSET 0x0 // USB command register offset\r
	42	#define EHC_USBSTS_OFFSET 0x04 // Statue register offset\r
	43	#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset\r
	44	#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset\r
	45	#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset\r
	46	#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset\r
	47	#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset\r
	48	#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r
	49	#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r
	50	\r
	51	#define EHC_FRAME_LEN 1024\r
	52	\r
	53	//\r
	54	// Register bit definition\r
	55	//\r
	56	#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r
	57	\r
	58	#define USBCMD_RUN 0x01 // Run/stop\r
	59	#define USBCMD_RESET 0x02 // Start the host controller reset\r
	60	#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r
	61	#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r
	62	#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r
	63	\r
	64	#define USBSTS_IAA 0x20 // Interrupt on async advance\r
	65	#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r
	66	#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r
	67	#define USBSTS_HALT 0x1000 // Host controller halted\r
	68	#define USBSTS_SYS_ERROR 0x10 // Host system error\r
	69	#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r
	70	// (write clean) bits in USBSTS register\r
	71	\r
	72	#define PORTSC_CONN 0x01 // Current Connect Status\r
	73	#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r
	74	#define PORTSC_ENABLED 0x04 // Port Enable / Disable\r
	75	#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r
	76	#define PORTSC_OVERCUR 0x10 // Over current Active\r
	77	#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r
	78	#define PORSTSC_RESUME 0x40 // Force Port Resume\r
	79	#define PORTSC_SUSPEND 0x80 // Port Suspend State\r
	80	#define PORTSC_RESET 0x100 // Port Reset\r
	81	#define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r
	82	#define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r
	83	#define PORTSC_POWER 0x1000 // Port Power\r
	84	#define PORTSC_OWNER 0x2000 // Port Owner\r
	85	#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r
	86	// they are WC (write clean)\r
	87	//\r
	88	// PCI Configuration Registers\r
	89	//\r
	90	#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r
	91	\r
	92	#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
	93	\r
	94	#define EHC_ADDR(High, QhHw32) \\r
	95	((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))\r
	96	\r
	97	#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
	98	\r
	99	//\r
	100	// Structure to map the hardware port states to the\r
	101	// UEFI's port states.\r
	102	//\r
	103	typedef struct {\r
	104	UINT16 HwState;\r
	105	UINT16 UefiState;\r
	106	} USB_PORT_STATE_MAP;\r
	107	\r
	108	//\r
	109	// Ehci Data and Ctrl Structures\r
	110	//\r
	111	#pragma pack(1)\r
	112	typedef struct {\r
	113	UINT8 ProgInterface;\r
	114	UINT8 SubClassCode;\r
	115	UINT8 BaseCode;\r
	116	} USB_CLASSC;\r
	117	#pragma pack()\r
	118	\r
	119	/**\r
	120	Read EHCI capability register.\r
	121	\r
	122	@param Ehc The EHCI device.\r
	123	@param Offset Capability register address.\r
	124	\r
	125	@return The register content.\r
	126	\r
	127	**/\r
	128	UINT32\r
	129	EhcReadCapRegister (\r
	130	IN USB2_HC_DEV *Ehc,\r
	131	IN UINT32 Offset\r
	132	);\r
	133	\r
	134	\r
	135	/**\r
	136	Read EHCI Operation register.\r
	137	\r
	138	@param Ehc The EHCI device.\r
	139	@param Offset The operation register offset.\r
	140	\r
	141	@return The register content.\r
	142	\r
	143	**/\r
	144	UINT32\r
	145	EhcReadOpReg (\r
	146	IN USB2_HC_DEV *Ehc,\r
	147	IN UINT32 Offset\r
	148	);\r
	149	\r
	150	\r
	151	/**\r
	152	Write the data to the EHCI operation register.\r
	153	\r
	154	@param Ehc The EHCI device.\r
	155	@param Offset EHCI operation register offset.\r
	156	@param Data The data to write.\r
	157	\r
	158	**/\r
	159	VOID\r
	160	EhcWriteOpReg (\r
	161	IN USB2_HC_DEV *Ehc,\r
	162	IN UINT32 Offset,\r
	163	IN UINT32 Data\r
	164	);\r
	165	\r
	166	/**\r
	167	Set one bit of the operational register while keeping other bits.\r
	168	\r
	169	@param Ehc The EHCI device.\r
	170	@param Offset The offset of the operational register.\r
	171	@param Bit The bit mask of the register to set.\r
	172	\r
	173	**/\r
	174	VOID\r
	175	EhcSetOpRegBit (\r
	176	IN USB2_HC_DEV *Ehc,\r
	177	IN UINT32 Offset,\r
	178	IN UINT32 Bit\r
	179	);\r
	180	\r
	181	/**\r
	182	Clear one bit of the operational register while keeping other bits.\r
	183	\r
	184	@param Ehc The EHCI device.\r
	185	@param Offset The offset of the operational register.\r
	186	@param Bit The bit mask of the register to clear.\r
	187	\r
	188	**/\r
	189	VOID\r
	190	EhcClearOpRegBit (\r
	191	IN USB2_HC_DEV *Ehc,\r
	192	IN UINT32 Offset,\r
	193	IN UINT32 Bit\r
	194	);\r
	195	\r
	196	/**\r
	197	Add support for UEFI Over Legacy (UoL) feature, stop\r
	198	the legacy USB SMI support.\r
	199	\r
	200	@param Ehc The EHCI device.\r
	201	\r
	202	**/\r
	203	VOID\r
	204	EhcClearLegacySupport (\r
	205	IN USB2_HC_DEV *Ehc\r
	206	);\r
	207	\r
	208	\r
	209	\r
	210	/**\r
	211	Set door bell and wait it to be ACKed by host controller.\r
	212	This function is used to synchronize with the hardware.\r
	213	\r
	214	@param Ehc The EHCI device.\r
	215	@param Timeout The time to wait before abort (in millisecond, ms).\r
	216	\r
	217	@retval EFI_SUCCESS Synchronized with the hardware.\r
	218	@retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r
	219	\r
	220	**/\r
	221	EFI_STATUS\r
	222	EhcSetAndWaitDoorBell (\r
	223	IN USB2_HC_DEV *Ehc,\r
	224	IN UINT32 Timeout\r
	225	);\r
	226	\r
	227	\r
	228	/**\r
	229	Clear all the interrutp status bits, these bits are Write-Clean.\r
	230	\r
	231	@param Ehc The EHCI device.\r
	232	\r
	233	**/\r
	234	VOID\r
	235	EhcAckAllInterrupt (\r
	236	IN USB2_HC_DEV *Ehc\r
	237	);\r
	238	\r
	239	\r
	240	\r
	241	/**\r
	242	Whether Ehc is halted.\r
	243	\r
	244	@param Ehc The EHCI device.\r
	245	\r
	246	@retval TRUE The controller is halted.\r
	247	@retval FALSE It isn't halted.\r
	248	\r
	249	**/\r
	250	BOOLEAN\r
	251	EhcIsHalt (\r
	252	IN USB2_HC_DEV *Ehc\r
	253	);\r
	254	\r
	255	\r
	256	/**\r
	257	Whether system error occurred.\r
	258	\r
	259	@param Ehc The EHCI device.\r
	260	\r
	261	@retval TRUE System error happened.\r
	262	@retval FALSE No system error.\r
	263	\r
	264	**/\r
	265	BOOLEAN\r
	266	EhcIsSysError (\r
	267	IN USB2_HC_DEV *Ehc\r
	268	);\r
	269	\r
	270	\r
	271	/**\r
	272	Reset the host controller.\r
	273	\r
	274	@param Ehc The EHCI device.\r
	275	@param Timeout Time to wait before abort (in millisecond, ms).\r
	276	\r
	277	@retval EFI_SUCCESS The host controller is reset.\r
	278	@return Others Failed to reset the host.\r
	279	\r
	280	**/\r
	281	EFI_STATUS\r
	282	EhcResetHC (\r
	283	IN USB2_HC_DEV *Ehc,\r
	284	IN UINT32 Timeout\r
	285	);\r
	286	\r
	287	\r
	288	/**\r
	289	Halt the host controller.\r
	290	\r
	291	@param Ehc The EHCI device.\r
	292	@param Timeout Time to wait before abort.\r
	293	\r
	294	@return EFI_SUCCESS The EHCI is halt.\r
	295	@return EFI_TIMEOUT Failed to halt the controller before Timeout.\r
	296	\r
	297	**/\r
	298	EFI_STATUS\r
	299	EhcHaltHC (\r
	300	IN USB2_HC_DEV *Ehc,\r
	301	IN UINT32 Timeout\r
	302	);\r
	303	\r
	304	\r
	305	/**\r
	306	Set the EHCI to run.\r
	307	\r
	308	@param Ehc The EHCI device.\r
	309	@param Timeout Time to wait before abort.\r
	310	\r
	311	@return EFI_SUCCESS The EHCI is running.\r
	312	@return Others Failed to set the EHCI to run.\r
	313	\r
	314	**/\r
	315	EFI_STATUS\r
	316	EhcRunHC (\r
	317	IN USB2_HC_DEV *Ehc,\r
	318	IN UINT32 Timeout\r
	319	);\r
	320	\r
	321	\r
	322	\r
	323	/**\r
	324	Initialize the HC hardware.\r
	325	EHCI spec lists the five things to do to initialize the hardware:\r
	326	1. Program CTRLDSSEGMENT\r
	327	2. Set USBINTR to enable interrupts\r
	328	3. Set periodic list base\r
	329	4. Set USBCMD, interrupt threshold, frame list size etc\r
	330	5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
	331	\r
	332	@param Ehc The EHCI device.\r
	333	\r
	334	@return EFI_SUCCESS The EHCI has come out of halt state.\r
	335	@return EFI_TIMEOUT Time out happened.\r
	336	\r
	337	**/\r
	338	EFI_STATUS\r
	339	EhcInitHC (\r
	340	IN USB2_HC_DEV *Ehc\r
	341	);\r
	342	\r
	343	#endif\r