[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / UhciReg.h

/** @file\r
\r
  The definition for UHCI register operation routines.\r
\r
Copyright (c) 2007 - 2008, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_UHCI_REG_H_\r
#define _EFI_UHCI_REG_H_\r
\r
#define BIT(a)  (1 << (a))\r
\r
typedef enum {\r
  UHCI_FRAME_NUM        = 1024,\r
\r
  //\r
  // Register offset and PCI related staff\r
  //\r
  CLASSC_OFFSET         = 0x09,\r
  USBBASE_OFFSET        = 0x20,\r
  USB_BAR_INDEX         = 4,\r
  PCI_CLASSC_PI_UHCI    = 0x00,\r
\r
  USBCMD_OFFSET         = 0,\r
  USBSTS_OFFSET         = 2,\r
  USBINTR_OFFSET        = 4,\r
  USBPORTSC_OFFSET      = 0x10,\r
  USB_FRAME_NO_OFFSET   = 6,\r
  USB_FRAME_BASE_OFFSET = 8,\r
  USB_EMULATION_OFFSET  = 0xC0,\r
\r
  //\r
  // Packet IDs\r
  //\r
  SETUP_PACKET_ID       = 0x2D,\r
  INPUT_PACKET_ID       = 0x69,\r
  OUTPUT_PACKET_ID      = 0xE1,\r
  ERROR_PACKET_ID       = 0x55,\r
\r
  //\r
  // USB port status and control bit definition.\r
  //\r
  USBPORTSC_CCS         = BIT(0),  // Current Connect Status\r
  USBPORTSC_CSC         = BIT(1),  // Connect Status Change\r
  USBPORTSC_PED         = BIT(2),  // Port Enable / Disable\r
  USBPORTSC_PEDC        = BIT(3),  // Port Enable / Disable Change\r
  USBPORTSC_LSL         = BIT(4),  // Line Status Low BIT\r
  USBPORTSC_LSH         = BIT(5),  // Line Status High BIT\r
  USBPORTSC_RD          = BIT(6),  // Resume Detect\r
  USBPORTSC_LSDA        = BIT(8),  // Low Speed Device Attached\r
  USBPORTSC_PR          = BIT(9),  // Port Reset\r
  USBPORTSC_SUSP        = BIT(12), // Suspend\r
\r
  //\r
  // UHCI Spec said it must implement 2 ports each host at least,\r
  // and if more, check whether the bit7 of PORTSC is always 1.\r
  // So here assume the max of port number each host is 16.\r
  //\r
  USB_MAX_ROOTHUB_PORT  = 0x0F,\r
  \r
  //\r
  // Command register bit definitions\r
  //\r
  USBCMD_RS             = BIT(0),  // Run/Stop\r
  USBCMD_HCRESET        = BIT(1),  // Host reset\r
  USBCMD_GRESET         = BIT(2),  // Global reset\r
  USBCMD_EGSM           = BIT(3),  // Global Suspend Mode\r
  USBCMD_FGR            = BIT(4),  // Force Global Resume\r
  USBCMD_SWDBG          = BIT(5),  // SW Debug mode\r
  USBCMD_CF             = BIT(6),  // Config Flag (sw only)\r
  USBCMD_MAXP           = BIT(7),  // Max Packet (0 = 32, 1 = 64)\r
\r
  //\r
  // USB Status register bit definitions\r
  //\r
  USBSTS_USBINT         = BIT(0),  // Interrupt due to IOC\r
  USBSTS_ERROR          = BIT(1),  // Interrupt due to error\r
  USBSTS_RD             = BIT(2),  // Resume Detect\r
  USBSTS_HSE            = BIT(3),  // Host System Error\r
  USBSTS_HCPE           = BIT(4),  // Host Controller Process Error\r
  USBSTS_HCH            = BIT(5),  // HC Halted\r
\r
  USBTD_ACTIVE          = BIT(7),  // TD is still active\r
  USBTD_STALLED         = BIT(6),  // TD is stalled\r
  USBTD_BUFFERR         = BIT(5),  // Buffer underflow or overflow\r
  USBTD_BABBLE          = BIT(4),  // Babble condition\r
  USBTD_NAK             = BIT(3),  // NAK is received\r
  USBTD_CRC             = BIT(2),  // CRC/Time out error\r
  USBTD_BITSTUFF        = BIT(1)  // Bit stuff error\r
}UHCI_REGISTER_OFFSET;\r
\r
\r
/**\r
  Read a UHCI register.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.\r
  @param  Offset       Register offset to USB_BAR_INDEX.\r
\r
  @return Content of register.\r
\r
**/\r
UINT16\r
UhciReadReg (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset\r
  )\r
;\r
\r
\r
\r
/**\r
  Write data to UHCI register.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.\r
  @param  Offset       Register offset to USB_BAR_INDEX.\r
  @param  Data         Data to write.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciWriteReg (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset,\r
  IN UINT16                  Data\r
  )\r
;\r
\r
\r
\r
/**\r
  Set a bit of the UHCI Register.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.\r
  @param  Offset       Register offset to USB_BAR_INDEX.\r
  @param  Bit          The bit to set.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciSetRegBit (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset,\r
  IN UINT16                  Bit\r
  )\r
;\r
\r
\r
\r
/**\r
  Clear a bit of the UHCI Register.\r
\r
  @param  PciIo        The PCI_IO protocol to access the PCI.\r
  @param  Offset       Register offset to USB_BAR_INDEX.\r
  @param  Bit          The bit to clear.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciClearRegBit (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset,\r
  IN UINT16                  Bit\r
  )\r
;\r
\r
\r
/**\r
  Clear all the interrutp status bits, these bits\r
  are Write-Clean.\r
\r
  @param  Uhc          The UHCI device.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciAckAllInterrupt (\r
  IN  USB_HC_DEV          *Uhc\r
  )\r
;\r
\r
\r
/**\r
  Stop the host controller.\r
\r
  @param  Uhc          The UHCI device.\r
  @param  Timeout      Max time allowed.\r
\r
  @retval EFI_SUCCESS  The host controller is stopped.\r
  @retval EFI_TIMEOUT  Failed to stop the host controller.\r
\r
**/\r
EFI_STATUS\r
UhciStopHc (\r
  IN USB_HC_DEV         *Uhc,\r
  IN UINTN              Timeout\r
  )\r
;\r
\r
\r
\r
/**\r
  Check whether the host controller operates well.\r
\r
  @param  PciIo        The PCI_IO protocol to use.\r
\r
  @retval TRUE         Host controller is working.\r
  @retval FALSE        Host controller is halted or system error.\r
\r
**/\r
BOOLEAN\r
UhciIsHcWorking (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo\r
  )\r
;\r
\r
\r
/**\r
  Set the UHCI frame list base address. It can't use\r
  UhciWriteReg which access memory in UINT16.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.\r
  @param  Addr         Address to set.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciSetFrameListBaseAddr (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN VOID                    *Addr\r
  )\r
;\r
\r
\r
/**\r
  Disable USB Emulation.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL protocol to use.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciTurnOffUsbEmulation (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo\r
  )\r
;\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	\r
	3	The definition for UHCI register operation routines.\r
	4	\r
	5	Copyright (c) 2007 - 2008, Intel Corporation\r
	6	All rights reserved. This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef _EFI_UHCI_REG_H_\r
	17	#define _EFI_UHCI_REG_H_\r
	18	\r
	19	#define BIT(a) (1 << (a))\r
	20	\r
	21	typedef enum {\r
	22	UHCI_FRAME_NUM = 1024,\r
	23	\r
	24	//\r
	25	// Register offset and PCI related staff\r
	26	//\r
	27	CLASSC_OFFSET = 0x09,\r
	28	USBBASE_OFFSET = 0x20,\r
	29	USB_BAR_INDEX = 4,\r
	30	PCI_CLASSC_PI_UHCI = 0x00,\r
	31	\r
	32	USBCMD_OFFSET = 0,\r
	33	USBSTS_OFFSET = 2,\r
	34	USBINTR_OFFSET = 4,\r
	35	USBPORTSC_OFFSET = 0x10,\r
	36	USB_FRAME_NO_OFFSET = 6,\r
	37	USB_FRAME_BASE_OFFSET = 8,\r
	38	USB_EMULATION_OFFSET = 0xC0,\r
	39	\r
	40	//\r
	41	// Packet IDs\r
	42	//\r
	43	SETUP_PACKET_ID = 0x2D,\r
	44	INPUT_PACKET_ID = 0x69,\r
	45	OUTPUT_PACKET_ID = 0xE1,\r
	46	ERROR_PACKET_ID = 0x55,\r
	47	\r
	48	//\r
	49	// USB port status and control bit definition.\r
	50	//\r
	51	USBPORTSC_CCS = BIT(0), // Current Connect Status\r
	52	USBPORTSC_CSC = BIT(1), // Connect Status Change\r
	53	USBPORTSC_PED = BIT(2), // Port Enable / Disable\r
	54	USBPORTSC_PEDC = BIT(3), // Port Enable / Disable Change\r
	55	USBPORTSC_LSL = BIT(4), // Line Status Low BIT\r
	56	USBPORTSC_LSH = BIT(5), // Line Status High BIT\r
	57	USBPORTSC_RD = BIT(6), // Resume Detect\r
	58	USBPORTSC_LSDA = BIT(8), // Low Speed Device Attached\r
	59	USBPORTSC_PR = BIT(9), // Port Reset\r
	60	USBPORTSC_SUSP = BIT(12), // Suspend\r
	61	\r
	62	//\r
	63	// UHCI Spec said it must implement 2 ports each host at least,\r
	64	// and if more, check whether the bit7 of PORTSC is always 1.\r
	65	// So here assume the max of port number each host is 16.\r
	66	//\r
	67	USB_MAX_ROOTHUB_PORT = 0x0F,\r
	68	\r
	69	//\r
	70	// Command register bit definitions\r
	71	//\r
	72	USBCMD_RS = BIT(0), // Run/Stop\r
	73	USBCMD_HCRESET = BIT(1), // Host reset\r
	74	USBCMD_GRESET = BIT(2), // Global reset\r
	75	USBCMD_EGSM = BIT(3), // Global Suspend Mode\r
	76	USBCMD_FGR = BIT(4), // Force Global Resume\r
	77	USBCMD_SWDBG = BIT(5), // SW Debug mode\r
	78	USBCMD_CF = BIT(6), // Config Flag (sw only)\r
	79	USBCMD_MAXP = BIT(7), // Max Packet (0 = 32, 1 = 64)\r
	80	\r
	81	//\r
	82	// USB Status register bit definitions\r
	83	//\r
	84	USBSTS_USBINT = BIT(0), // Interrupt due to IOC\r
	85	USBSTS_ERROR = BIT(1), // Interrupt due to error\r
	86	USBSTS_RD = BIT(2), // Resume Detect\r
	87	USBSTS_HSE = BIT(3), // Host System Error\r
	88	USBSTS_HCPE = BIT(4), // Host Controller Process Error\r
	89	USBSTS_HCH = BIT(5), // HC Halted\r
	90	\r
	91	USBTD_ACTIVE = BIT(7), // TD is still active\r
	92	USBTD_STALLED = BIT(6), // TD is stalled\r
	93	USBTD_BUFFERR = BIT(5), // Buffer underflow or overflow\r
	94	USBTD_BABBLE = BIT(4), // Babble condition\r
	95	USBTD_NAK = BIT(3), // NAK is received\r
	96	USBTD_CRC = BIT(2), // CRC/Time out error\r
	97	USBTD_BITSTUFF = BIT(1) // Bit stuff error\r
	98	}UHCI_REGISTER_OFFSET;\r
	99	\r
	100	\r
	101	/**\r
	102	Read a UHCI register.\r
	103	\r
	104	@param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
	105	@param Offset Register offset to USB_BAR_INDEX.\r
	106	\r
	107	@return Content of register.\r
	108	\r
	109	**/\r
	110	UINT16\r
	111	UhciReadReg (\r
	112	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	113	IN UINT32 Offset\r
	114	)\r
	115	;\r
	116	\r
	117	\r
	118	\r
	119	/**\r
	120	Write data to UHCI register.\r
	121	\r
	122	@param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
	123	@param Offset Register offset to USB_BAR_INDEX.\r
	124	@param Data Data to write.\r
	125	\r
	126	@return None.\r
	127	\r
	128	**/\r
	129	VOID\r
	130	UhciWriteReg (\r
	131	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	132	IN UINT32 Offset,\r
	133	IN UINT16 Data\r
	134	)\r
	135	;\r
	136	\r
	137	\r
	138	\r
	139	/**\r
	140	Set a bit of the UHCI Register.\r
	141	\r
	142	@param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
	143	@param Offset Register offset to USB_BAR_INDEX.\r
	144	@param Bit The bit to set.\r
	145	\r
	146	@return None.\r
	147	\r
	148	**/\r
	149	VOID\r
	150	UhciSetRegBit (\r
	151	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	152	IN UINT32 Offset,\r
	153	IN UINT16 Bit\r
	154	)\r
	155	;\r
	156	\r
	157	\r
	158	\r
	159	/**\r
	160	Clear a bit of the UHCI Register.\r
	161	\r
	162	@param PciIo The PCI_IO protocol to access the PCI.\r
	163	@param Offset Register offset to USB_BAR_INDEX.\r
	164	@param Bit The bit to clear.\r
	165	\r
	166	@return None.\r
	167	\r
	168	**/\r
	169	VOID\r
	170	UhciClearRegBit (\r
	171	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	172	IN UINT32 Offset,\r
	173	IN UINT16 Bit\r
	174	)\r
	175	;\r
	176	\r
	177	\r
	178	/**\r
	179	Clear all the interrutp status bits, these bits\r
	180	are Write-Clean.\r
	181	\r
	182	@param Uhc The UHCI device.\r
	183	\r
	184	@return None.\r
	185	\r
	186	**/\r
	187	VOID\r
	188	UhciAckAllInterrupt (\r
	189	IN USB_HC_DEV *Uhc\r
	190	)\r
	191	;\r
	192	\r
	193	\r
	194	/**\r
	195	Stop the host controller.\r
	196	\r
	197	@param Uhc The UHCI device.\r
	198	@param Timeout Max time allowed.\r
	199	\r
	200	@retval EFI_SUCCESS The host controller is stopped.\r
	201	@retval EFI_TIMEOUT Failed to stop the host controller.\r
	202	\r
	203	**/\r
	204	EFI_STATUS\r
	205	UhciStopHc (\r
	206	IN USB_HC_DEV *Uhc,\r
	207	IN UINTN Timeout\r
	208	)\r
	209	;\r
	210	\r
	211	\r
	212	\r
	213	/**\r
	214	Check whether the host controller operates well.\r
	215	\r
	216	@param PciIo The PCI_IO protocol to use.\r
	217	\r
	218	@retval TRUE Host controller is working.\r
	219	@retval FALSE Host controller is halted or system error.\r
	220	\r
	221	**/\r
	222	BOOLEAN\r
	223	UhciIsHcWorking (\r
	224	IN EFI_PCI_IO_PROTOCOL *PciIo\r
	225	)\r
	226	;\r
	227	\r
	228	\r
	229	/**\r
	230	Set the UHCI frame list base address. It can't use\r
	231	UhciWriteReg which access memory in UINT16.\r
	232	\r
	233	@param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
	234	@param Addr Address to set.\r
	235	\r
	236	@return None.\r
	237	\r
	238	**/\r
	239	VOID\r
	240	UhciSetFrameListBaseAddr (\r
	241	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	242	IN VOID *Addr\r
	243	)\r
	244	;\r
	245	\r
	246	\r
	247	/**\r
	248	Disable USB Emulation.\r
	249	\r
	250	@param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.\r
	251	\r
	252	@return None.\r
	253	\r
	254	**/\r
	255	VOID\r
	256	UhciTurnOffUsbEmulation (\r
	257	IN EFI_PCI_IO_PROTOCOL *PciIo\r
	258	)\r
	259	;\r
	260	#endif\r