MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h

   1 /** @file
   2
   3   The definition for UHCI register operation routines.
   4
   5 Copyright (c) 2007 - 2008, Intel Corporation
   6 All rights reserved. This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _EFI_UHCI_REG_H_
  17 #define _EFI_UHCI_REG_H_
  18
  19 #define BIT(a)  (1 << (a))
  20
  21 typedef enum {
  22   UHCI_FRAME_NUM        = 1024,
  23
  24   //
  25   // Register offset and PCI related staff
  26   //
  27   CLASSC_OFFSET         = 0x09,
  28   USBBASE_OFFSET        = 0x20,
  29   USB_BAR_INDEX         = 4,
  30   PCI_CLASSC_PI_UHCI    = 0x00,
  31
  32   USBCMD_OFFSET         = 0,
  33   USBSTS_OFFSET         = 2,
  34   USBINTR_OFFSET        = 4,
  35   USBPORTSC_OFFSET      = 0x10,
  36   USB_FRAME_NO_OFFSET   = 6,
  37   USB_FRAME_BASE_OFFSET = 8,
  38   USB_EMULATION_OFFSET  = 0xC0,
  39
  40   //
  41   // Packet IDs
  42   //
  43   SETUP_PACKET_ID       = 0x2D,
  44   INPUT_PACKET_ID       = 0x69,
  45   OUTPUT_PACKET_ID      = 0xE1,
  46   ERROR_PACKET_ID       = 0x55,
  47
  48   //
  49   // USB port status and control bit definition.
  50   //
  51   USBPORTSC_CCS         = BIT(0),  // Current Connect Status
  52   USBPORTSC_CSC         = BIT(1),  // Connect Status Change
  53   USBPORTSC_PED         = BIT(2),  // Port Enable / Disable
  54   USBPORTSC_PEDC        = BIT(3),  // Port Enable / Disable Change
  55   USBPORTSC_LSL         = BIT(4),  // Line Status Low BIT
  56   USBPORTSC_LSH         = BIT(5),  // Line Status High BIT
  57   USBPORTSC_RD          = BIT(6),  // Resume Detect
  58   USBPORTSC_LSDA        = BIT(8),  // Low Speed Device Attached
  59   USBPORTSC_PR          = BIT(9),  // Port Reset
  60   USBPORTSC_SUSP        = BIT(12), // Suspend
  61
  62   //
  63   // UHCI Spec said it must implement 2 ports each host at least,
  64   // and if more, check whether the bit7 of PORTSC is always 1.
  65   // So here assume the max of port number each host is 16.
  66   //
  67   USB_MAX_ROOTHUB_PORT  = 0x0F,
  68
  69   //
  70   // Command register bit definitions
  71   //
  72   USBCMD_RS             = BIT(0),  // Run/Stop
  73   USBCMD_HCRESET        = BIT(1),  // Host reset
  74   USBCMD_GRESET         = BIT(2),  // Global reset
  75   USBCMD_EGSM           = BIT(3),  // Global Suspend Mode
  76   USBCMD_FGR            = BIT(4),  // Force Global Resume
  77   USBCMD_SWDBG          = BIT(5),  // SW Debug mode
  78   USBCMD_CF             = BIT(6),  // Config Flag (sw only)
  79   USBCMD_MAXP           = BIT(7),  // Max Packet (0 = 32, 1 = 64)
  80
  81   //
  82   // USB Status register bit definitions
  83   //
  84   USBSTS_USBINT         = BIT(0),  // Interrupt due to IOC
  85   USBSTS_ERROR          = BIT(1),  // Interrupt due to error
  86   USBSTS_RD             = BIT(2),  // Resume Detect
  87   USBSTS_HSE            = BIT(3),  // Host System Error
  88   USBSTS_HCPE           = BIT(4),  // Host Controller Process Error
  89   USBSTS_HCH            = BIT(5),  // HC Halted
  90
  91   USBTD_ACTIVE          = BIT(7),  // TD is still active
  92   USBTD_STALLED         = BIT(6),  // TD is stalled
  93   USBTD_BUFFERR         = BIT(5),  // Buffer underflow or overflow
  94   USBTD_BABBLE          = BIT(4),  // Babble condition
  95   USBTD_NAK             = BIT(3),  // NAK is received
  96   USBTD_CRC             = BIT(2),  // CRC/Time out error
  97   USBTD_BITSTUFF        = BIT(1)  // Bit stuff error
  98 }UHCI_REGISTER_OFFSET;
  99
 100
 101 /**
 102   Read a UHCI register.
 103
 104   @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.
 105   @param  Offset       Register offset to USB_BAR_INDEX.
 106
 107   @return Content of register.
 108
 109 **/
 110 UINT16
 111 UhciReadReg (
 112   IN EFI_PCI_IO_PROTOCOL     *PciIo,
 113   IN UINT32                  Offset
 114   )
 115 ;
 116
 117
 118
 119 /**
 120   Write data to UHCI register.
 121
 122   @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.
 123   @param  Offset       Register offset to USB_BAR_INDEX.
 124   @param  Data         Data to write.
 125
 126   @return None.
 127
 128 **/
 129 VOID
 130 UhciWriteReg (
 131   IN EFI_PCI_IO_PROTOCOL     *PciIo,
 132   IN UINT32                  Offset,
 133   IN UINT16                  Data
 134   )
 135 ;
 136
 137
 138
 139 /**
 140   Set a bit of the UHCI Register.
 141
 142   @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.
 143   @param  Offset       Register offset to USB_BAR_INDEX.
 144   @param  Bit          The bit to set.
 145
 146   @return None.
 147
 148 **/
 149 VOID
 150 UhciSetRegBit (
 151   IN EFI_PCI_IO_PROTOCOL     *PciIo,
 152   IN UINT32                  Offset,
 153   IN UINT16                  Bit
 154   )
 155 ;
 156
 157
 158
 159 /**
 160   Clear a bit of the UHCI Register.
 161
 162   @param  PciIo        The PCI_IO protocol to access the PCI.
 163   @param  Offset       Register offset to USB_BAR_INDEX.
 164   @param  Bit          The bit to clear.
 165
 166   @return None.
 167
 168 **/
 169 VOID
 170 UhciClearRegBit (
 171   IN EFI_PCI_IO_PROTOCOL     *PciIo,
 172   IN UINT32                  Offset,
 173   IN UINT16                  Bit
 174   )
 175 ;
 176
 177
 178 /**
 179   Clear all the interrutp status bits, these bits
 180   are Write-Clean.
 181
 182   @param  Uhc          The UHCI device.
 183
 184   @return None.
 185
 186 **/
 187 VOID
 188 UhciAckAllInterrupt (
 189   IN  USB_HC_DEV          *Uhc
 190   )
 191 ;
 192
 193
 194 /**
 195   Stop the host controller.
 196
 197   @param  Uhc          The UHCI device.
 198   @param  Timeout      Max time allowed.
 199
 200   @retval EFI_SUCCESS  The host controller is stopped.
 201   @retval EFI_TIMEOUT  Failed to stop the host controller.
 202
 203 **/
 204 EFI_STATUS
 205 UhciStopHc (
 206   IN USB_HC_DEV         *Uhc,
 207   IN UINTN              Timeout
 208   )
 209 ;
 210
 211
 212
 213 /**
 214   Check whether the host controller operates well.
 215
 216   @param  PciIo        The PCI_IO protocol to use.
 217
 218   @retval TRUE         Host controller is working.
 219   @retval FALSE        Host controller is halted or system error.
 220
 221 **/
 222 BOOLEAN
 223 UhciIsHcWorking (
 224   IN EFI_PCI_IO_PROTOCOL     *PciIo
 225   )
 226 ;
 227
 228
 229 /**
 230   Set the UHCI frame list base address. It can't use
 231   UhciWriteReg which access memory in UINT16.
 232
 233   @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.
 234   @param  Addr         Address to set.
 235
 236   @return None.
 237
 238 **/
 239 VOID
 240 UhciSetFrameListBaseAddr (
 241   IN EFI_PCI_IO_PROTOCOL     *PciIo,
 242   IN VOID                    *Addr
 243   )
 244 ;
 245
 246
 247 /**
 248   Disable USB Emulation.
 249
 250   @param  PciIo        The EFI_PCI_IO_PROTOCOL protocol to use.
 251
 252   @return None.
 253
 254 **/
 255 VOID
 256 UhciTurnOffUsbEmulation (
 257   IN EFI_PCI_IO_PROTOCOL     *PciIo
 258   )
 259 ;
 260 #endif