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1 | /** @file\r | |
2 | Protocol to describe overrides required to support non-standard SDHCI\r | |
3 | implementations\r | |
4 | \r | |
5 | Copyright (c) 2017 - 2018, Linaro, Ltd. All rights reserved.<BR>\r | |
6 | \r | |
7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
8 | \r | |
9 | **/\r | |
10 | \r | |
11 | #ifndef __SD_MMC_OVERRIDE_H__\r | |
12 | #define __SD_MMC_OVERRIDE_H__\r | |
13 | \r | |
14 | #include <Protocol/SdMmcPassThru.h>\r | |
15 | \r | |
16 | #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \\r | |
17 | { 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23, 0x23 } }\r | |
18 | \r | |
19 | #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x3\r | |
20 | \r | |
21 | typedef struct _EDKII_SD_MMC_OVERRIDE EDKII_SD_MMC_OVERRIDE;\r | |
22 | \r | |
23 | #define EDKII_SD_MMC_BUS_WIDTH_IGNORE MAX_UINT8\r | |
24 | #define EDKII_SD_MMC_CLOCK_FREQ_IGNORE MAX_UINT32\r | |
25 | #define EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE MAX_UINT8\r | |
26 | \r | |
27 | typedef enum {\r | |
28 | SdDriverStrengthTypeB = 0,\r | |
29 | SdDriverStrengthTypeA,\r | |
30 | SdDriverStrengthTypeC,\r | |
31 | SdDriverStrengthTypeD,\r | |
32 | SdDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE\r | |
33 | } SD_DRIVER_STRENGTH_TYPE;\r | |
34 | \r | |
35 | typedef enum {\r | |
36 | EmmcDriverStrengthType0 = 0,\r | |
37 | EmmcDriverStrengthType1,\r | |
38 | EmmcDriverStrengthType2,\r | |
39 | EmmcDriverStrengthType3,\r | |
40 | EmmcDriverStrengthType4,\r | |
41 | EmmcDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE\r | |
42 | } EMMC_DRIVER_STRENGTH_TYPE;\r | |
43 | \r | |
44 | typedef union {\r | |
45 | SD_DRIVER_STRENGTH_TYPE Sd;\r | |
46 | EMMC_DRIVER_STRENGTH_TYPE Emmc;\r | |
47 | } EDKII_SD_MMC_DRIVER_STRENGTH;\r | |
48 | \r | |
49 | typedef struct {\r | |
50 | //\r | |
51 | // The target width of the bus. If user tells driver to ignore it\r | |
52 | // or specifies unsupported width driver will choose highest supported\r | |
53 | // bus width for a given mode.\r | |
54 | //\r | |
55 | UINT8 BusWidth;\r | |
56 | //\r | |
57 | // The target clock frequency of the bus in MHz. If user tells driver to ignore\r | |
58 | // it or specifies unsupported frequency driver will choose highest supported\r | |
59 | // clock frequency for a given mode.\r | |
60 | //\r | |
61 | UINT32 ClockFreq;\r | |
62 | //\r | |
63 | // The target driver strength of the bus. If user tells driver to\r | |
64 | // ignore it or specifies unsupported driver strength, driver will\r | |
65 | // default to Type0 for eMMC cards and TypeB for SD cards. Driver strength\r | |
66 | // setting is only considered if chosen bus timing supports them.\r | |
67 | //\r | |
68 | EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;\r | |
69 | } EDKII_SD_MMC_OPERATING_PARAMETERS;\r | |
70 | \r | |
71 | typedef enum {\r | |
72 | SdMmcSdDs,\r | |
73 | SdMmcSdHs,\r | |
74 | SdMmcUhsSdr12,\r | |
75 | SdMmcUhsSdr25,\r | |
76 | SdMmcUhsSdr50,\r | |
77 | SdMmcUhsDdr50,\r | |
78 | SdMmcUhsSdr104,\r | |
79 | SdMmcMmcLegacy,\r | |
80 | SdMmcMmcHsSdr,\r | |
81 | SdMmcMmcHsDdr,\r | |
82 | SdMmcMmcHs200,\r | |
83 | SdMmcMmcHs400,\r | |
84 | } SD_MMC_BUS_MODE;\r | |
85 | \r | |
86 | typedef enum {\r | |
87 | EdkiiSdMmcResetPre,\r | |
88 | EdkiiSdMmcResetPost,\r | |
89 | EdkiiSdMmcInitHostPre,\r | |
90 | EdkiiSdMmcInitHostPost,\r | |
91 | EdkiiSdMmcUhsSignaling,\r | |
92 | EdkiiSdMmcSwitchClockFreqPost,\r | |
93 | EdkiiSdMmcGetOperatingParam\r | |
94 | } EDKII_SD_MMC_PHASE_TYPE;\r | |
95 | \r | |
96 | /**\r | |
97 | Override function for SDHCI capability bits\r | |
98 | \r | |
99 | @param[in] ControllerHandle The EFI_HANDLE of the controller.\r | |
100 | @param[in] Slot The 0 based slot index.\r | |
101 | @param[in,out] SdMmcHcSlotCapability The SDHCI capability structure.\r | |
102 | @param[in,out] BaseClkFreq The base clock frequency value that\r | |
103 | optionally can be updated.\r | |
104 | \r | |
105 | @retval EFI_SUCCESS The override function completed successfully.\r | |
106 | @retval EFI_NOT_FOUND The specified controller or slot does not exist.\r | |
107 | @retval EFI_INVALID_PARAMETER SdMmcHcSlotCapability is NULL\r | |
108 | \r | |
109 | **/\r | |
110 | typedef\r | |
111 | EFI_STATUS\r | |
112 | (EFIAPI * EDKII_SD_MMC_CAPABILITY) (\r | |
113 | IN EFI_HANDLE ControllerHandle,\r | |
114 | IN UINT8 Slot,\r | |
115 | IN OUT VOID *SdMmcHcSlotCapability,\r | |
116 | IN OUT UINT32 *BaseClkFreq\r | |
117 | );\r | |
118 | \r | |
119 | /**\r | |
120 | Override function for SDHCI controller operations\r | |
121 | \r | |
122 | @param[in] ControllerHandle The EFI_HANDLE of the controller.\r | |
123 | @param[in] Slot The 0 based slot index.\r | |
124 | @param[in] PhaseType The type of operation and whether the\r | |
125 | hook is invoked right before (pre) or\r | |
126 | right after (post)\r | |
127 | @param[in,out] PhaseData The pointer to a phase-specific data.\r | |
128 | \r | |
129 | @retval EFI_SUCCESS The override function completed successfully.\r | |
130 | @retval EFI_NOT_FOUND The specified controller or slot does not exist.\r | |
131 | @retval EFI_INVALID_PARAMETER PhaseType is invalid\r | |
132 | \r | |
133 | **/\r | |
134 | typedef\r | |
135 | EFI_STATUS\r | |
136 | (EFIAPI * EDKII_SD_MMC_NOTIFY_PHASE) (\r | |
137 | IN EFI_HANDLE ControllerHandle,\r | |
138 | IN UINT8 Slot,\r | |
139 | IN EDKII_SD_MMC_PHASE_TYPE PhaseType,\r | |
140 | IN OUT VOID *PhaseData\r | |
141 | );\r | |
142 | \r | |
143 | struct _EDKII_SD_MMC_OVERRIDE {\r | |
144 | //\r | |
145 | // Protocol version of this implementation\r | |
146 | //\r | |
147 | UINTN Version;\r | |
148 | //\r | |
149 | // Callback to override SD/MMC host controller capability bits\r | |
150 | //\r | |
151 | EDKII_SD_MMC_CAPABILITY Capability;\r | |
152 | //\r | |
153 | // Callback to invoke SD/MMC override hooks\r | |
154 | //\r | |
155 | EDKII_SD_MMC_NOTIFY_PHASE NotifyPhase;\r | |
156 | };\r | |
157 | \r | |
158 | extern EFI_GUID gEdkiiSdMmcOverrideProtocolGuid;\r | |
159 | \r | |
160 | #endif\r |