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1 | /** @file\r | |
2 | Provides services to access PCI Configuration Space using the MMIO PCI Express window.\r | |
3 | \r | |
4 | This library is identical to the PCI Library, except the access method for performing PCI \r | |
5 | configuration cycles must be through the 256 MB PCI Express MMIO window whose base address\r | |
6 | is defined by PcdPciExpressBaseAddress.\r | |
7 | \r | |
8 | Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r | |
9 | This program and the accompanying materials\r | |
10 | are licensed and made available under the terms and conditions of the BSD License\r | |
11 | which accompanies this distribution. The full text of the license may be found at\r | |
12 | http://opensource.org/licenses/bsd-license.php\r | |
13 | \r | |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | #ifndef __PCI_EXPRESS_LIB_H__\r | |
20 | #define __PCI_EXPRESS_LIB_H__\r | |
21 | \r | |
22 | /**\r | |
23 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
24 | address that can be passed to the PCI Library functions.\r | |
25 | \r | |
26 | Computes an address that is compatible with the PCI Library functions. The\r | |
27 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r | |
28 | the generation of the address.\r | |
29 | \r | |
30 | @param Bus PCI Bus number. Range 0..255.\r | |
31 | @param Device PCI Device number. Range 0..31.\r | |
32 | @param Function PCI Function number. Range 0..7.\r | |
33 | @param Register PCI Register number. Range 0..4095.\r | |
34 | \r | |
35 | @return The encode PCI address.\r | |
36 | \r | |
37 | **/\r | |
38 | #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))\r | |
39 | \r | |
40 | /**\r | |
41 | Registers a PCI device so PCI configuration registers may be accessed after \r | |
42 | SetVirtualAddressMap().\r | |
43 | \r | |
44 | Registers the PCI device specified by Address so all the PCI configuration \r | |
45 | registers associated with that PCI device may be accessed after SetVirtualAddressMap() \r | |
46 | is called.\r | |
47 | \r | |
48 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
49 | \r | |
50 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
51 | Register.\r | |
52 | \r | |
53 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
54 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
55 | after ExitBootServices().\r | |
56 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
57 | at runtime could not be mapped.\r | |
58 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
59 | complete the registration.\r | |
60 | \r | |
61 | **/\r | |
62 | RETURN_STATUS\r | |
63 | EFIAPI\r | |
64 | PciExpressRegisterForRuntimeAccess (\r | |
65 | IN UINTN Address\r | |
66 | );\r | |
67 | \r | |
68 | /**\r | |
69 | Reads an 8-bit PCI configuration register.\r | |
70 | \r | |
71 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
72 | This function must guarantee that all PCI read and write operations are\r | |
73 | serialized.\r | |
74 | \r | |
75 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
76 | \r | |
77 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
78 | Register.\r | |
79 | \r | |
80 | @return The read value from the PCI configuration register.\r | |
81 | \r | |
82 | **/\r | |
83 | UINT8\r | |
84 | EFIAPI\r | |
85 | PciExpressRead8 (\r | |
86 | IN UINTN Address\r | |
87 | );\r | |
88 | \r | |
89 | /**\r | |
90 | Writes an 8-bit PCI configuration register.\r | |
91 | \r | |
92 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
93 | value specified by Value. Value is returned. This function must guarantee\r | |
94 | that all PCI read and write operations are serialized.\r | |
95 | \r | |
96 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
97 | \r | |
98 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
99 | Register.\r | |
100 | @param Value The value to write.\r | |
101 | \r | |
102 | @return The value written to the PCI configuration register.\r | |
103 | \r | |
104 | **/\r | |
105 | UINT8\r | |
106 | EFIAPI\r | |
107 | PciExpressWrite8 (\r | |
108 | IN UINTN Address,\r | |
109 | IN UINT8 Value\r | |
110 | );\r | |
111 | \r | |
112 | /**\r | |
113 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
114 | an 8-bit value.\r | |
115 | \r | |
116 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
117 | bitwise OR between the read result and the value specified by\r | |
118 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
119 | specified by Address. The value written to the PCI configuration register is\r | |
120 | returned. This function must guarantee that all PCI read and write operations\r | |
121 | are serialized.\r | |
122 | \r | |
123 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
124 | \r | |
125 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
126 | Register.\r | |
127 | @param OrData The value to OR with the PCI configuration register.\r | |
128 | \r | |
129 | @return The value written back to the PCI configuration register.\r | |
130 | \r | |
131 | **/\r | |
132 | UINT8\r | |
133 | EFIAPI\r | |
134 | PciExpressOr8 (\r | |
135 | IN UINTN Address,\r | |
136 | IN UINT8 OrData\r | |
137 | );\r | |
138 | \r | |
139 | /**\r | |
140 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
141 | value.\r | |
142 | \r | |
143 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
144 | bitwise AND between the read result and the value specified by AndData, and\r | |
145 | writes the result to the 8-bit PCI configuration register specified by\r | |
146 | Address. The value written to the PCI configuration register is returned.\r | |
147 | This function must guarantee that all PCI read and write operations are\r | |
148 | serialized.\r | |
149 | \r | |
150 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
151 | \r | |
152 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
153 | Register.\r | |
154 | @param AndData The value to AND with the PCI configuration register.\r | |
155 | \r | |
156 | @return The value written back to the PCI configuration register.\r | |
157 | \r | |
158 | **/\r | |
159 | UINT8\r | |
160 | EFIAPI\r | |
161 | PciExpressAnd8 (\r | |
162 | IN UINTN Address,\r | |
163 | IN UINT8 AndData\r | |
164 | );\r | |
165 | \r | |
166 | /**\r | |
167 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
168 | value, followed a bitwise OR with another 8-bit value.\r | |
169 | \r | |
170 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
171 | bitwise AND between the read result and the value specified by AndData,\r | |
172 | performs a bitwise OR between the result of the AND operation and\r | |
173 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
174 | configuration register specified by Address. The value written to the PCI\r | |
175 | configuration register is returned. This function must guarantee that all PCI\r | |
176 | read and write operations are serialized.\r | |
177 | \r | |
178 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
179 | \r | |
180 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
181 | Register.\r | |
182 | @param AndData The value to AND with the PCI configuration register.\r | |
183 | @param OrData The value to OR with the result of the AND operation.\r | |
184 | \r | |
185 | @return The value written back to the PCI configuration register.\r | |
186 | \r | |
187 | **/\r | |
188 | UINT8\r | |
189 | EFIAPI\r | |
190 | PciExpressAndThenOr8 (\r | |
191 | IN UINTN Address,\r | |
192 | IN UINT8 AndData,\r | |
193 | IN UINT8 OrData\r | |
194 | );\r | |
195 | \r | |
196 | /**\r | |
197 | Reads a bit field of a PCI configuration register.\r | |
198 | \r | |
199 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
200 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
201 | returned.\r | |
202 | \r | |
203 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
204 | If StartBit is greater than 7, then ASSERT().\r | |
205 | If EndBit is greater than 7, then ASSERT().\r | |
206 | If EndBit is less than StartBit, then ASSERT().\r | |
207 | \r | |
208 | @param Address PCI configuration register to read.\r | |
209 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
210 | Range 0..7.\r | |
211 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
212 | Range 0..7.\r | |
213 | \r | |
214 | @return The value of the bit field read from the PCI configuration register.\r | |
215 | \r | |
216 | **/\r | |
217 | UINT8\r | |
218 | EFIAPI\r | |
219 | PciExpressBitFieldRead8 (\r | |
220 | IN UINTN Address,\r | |
221 | IN UINTN StartBit,\r | |
222 | IN UINTN EndBit\r | |
223 | );\r | |
224 | \r | |
225 | /**\r | |
226 | Writes a bit field to a PCI configuration register.\r | |
227 | \r | |
228 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
229 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
230 | destination PCI configuration register are preserved. The new value of the\r | |
231 | 8-bit register is returned.\r | |
232 | \r | |
233 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
234 | If StartBit is greater than 7, then ASSERT().\r | |
235 | If EndBit is greater than 7, then ASSERT().\r | |
236 | If EndBit is less than StartBit, then ASSERT().\r | |
237 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
238 | \r | |
239 | @param Address PCI configuration register to write.\r | |
240 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
241 | Range 0..7.\r | |
242 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
243 | Range 0..7.\r | |
244 | @param Value New value of the bit field.\r | |
245 | \r | |
246 | @return The value written back to the PCI configuration register.\r | |
247 | \r | |
248 | **/\r | |
249 | UINT8\r | |
250 | EFIAPI\r | |
251 | PciExpressBitFieldWrite8 (\r | |
252 | IN UINTN Address,\r | |
253 | IN UINTN StartBit,\r | |
254 | IN UINTN EndBit,\r | |
255 | IN UINT8 Value\r | |
256 | );\r | |
257 | \r | |
258 | /**\r | |
259 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
260 | writes the result back to the bit field in the 8-bit port.\r | |
261 | \r | |
262 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
263 | bitwise OR between the read result and the value specified by\r | |
264 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
265 | specified by Address. The value written to the PCI configuration register is\r | |
266 | returned. This function must guarantee that all PCI read and write operations\r | |
267 | are serialized. Extra left bits in OrData are stripped.\r | |
268 | \r | |
269 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
270 | If StartBit is greater than 7, then ASSERT().\r | |
271 | If EndBit is greater than 7, then ASSERT().\r | |
272 | If EndBit is less than StartBit, then ASSERT().\r | |
273 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
274 | \r | |
275 | @param Address PCI configuration register to write.\r | |
276 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
277 | Range 0..7.\r | |
278 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
279 | Range 0..7.\r | |
280 | @param OrData The value to OR with the PCI configuration register.\r | |
281 | \r | |
282 | @return The value written back to the PCI configuration register.\r | |
283 | \r | |
284 | **/\r | |
285 | UINT8\r | |
286 | EFIAPI\r | |
287 | PciExpressBitFieldOr8 (\r | |
288 | IN UINTN Address,\r | |
289 | IN UINTN StartBit,\r | |
290 | IN UINTN EndBit,\r | |
291 | IN UINT8 OrData\r | |
292 | );\r | |
293 | \r | |
294 | /**\r | |
295 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
296 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
297 | \r | |
298 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
299 | bitwise AND between the read result and the value specified by AndData, and\r | |
300 | writes the result to the 8-bit PCI configuration register specified by\r | |
301 | Address. The value written to the PCI configuration register is returned.\r | |
302 | This function must guarantee that all PCI read and write operations are\r | |
303 | serialized. Extra left bits in AndData are stripped.\r | |
304 | \r | |
305 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
306 | If StartBit is greater than 7, then ASSERT().\r | |
307 | If EndBit is greater than 7, then ASSERT().\r | |
308 | If EndBit is less than StartBit, then ASSERT().\r | |
309 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
310 | \r | |
311 | @param Address PCI configuration register to write.\r | |
312 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
313 | Range 0..7.\r | |
314 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
315 | Range 0..7.\r | |
316 | @param AndData The value to AND with the PCI configuration register.\r | |
317 | \r | |
318 | @return The value written back to the PCI configuration register.\r | |
319 | \r | |
320 | **/\r | |
321 | UINT8\r | |
322 | EFIAPI\r | |
323 | PciExpressBitFieldAnd8 (\r | |
324 | IN UINTN Address,\r | |
325 | IN UINTN StartBit,\r | |
326 | IN UINTN EndBit,\r | |
327 | IN UINT8 AndData\r | |
328 | );\r | |
329 | \r | |
330 | /**\r | |
331 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
332 | bitwise OR, and writes the result back to the bit field in the\r | |
333 | 8-bit port.\r | |
334 | \r | |
335 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
336 | bitwise AND followed by a bitwise OR between the read result and\r | |
337 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
338 | configuration register specified by Address. The value written to the PCI\r | |
339 | configuration register is returned. This function must guarantee that all PCI\r | |
340 | read and write operations are serialized. Extra left bits in both AndData and\r | |
341 | OrData are stripped.\r | |
342 | \r | |
343 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
344 | If StartBit is greater than 7, then ASSERT().\r | |
345 | If EndBit is greater than 7, then ASSERT().\r | |
346 | If EndBit is less than StartBit, then ASSERT().\r | |
347 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
348 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
349 | \r | |
350 | @param Address PCI configuration register to write.\r | |
351 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
352 | Range 0..7.\r | |
353 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
354 | Range 0..7.\r | |
355 | @param AndData The value to AND with the PCI configuration register.\r | |
356 | @param OrData The value to OR with the result of the AND operation.\r | |
357 | \r | |
358 | @return The value written back to the PCI configuration register.\r | |
359 | \r | |
360 | **/\r | |
361 | UINT8\r | |
362 | EFIAPI\r | |
363 | PciExpressBitFieldAndThenOr8 (\r | |
364 | IN UINTN Address,\r | |
365 | IN UINTN StartBit,\r | |
366 | IN UINTN EndBit,\r | |
367 | IN UINT8 AndData,\r | |
368 | IN UINT8 OrData\r | |
369 | );\r | |
370 | \r | |
371 | /**\r | |
372 | Reads a 16-bit PCI configuration register.\r | |
373 | \r | |
374 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
375 | This function must guarantee that all PCI read and write operations are\r | |
376 | serialized.\r | |
377 | \r | |
378 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
379 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
380 | \r | |
381 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
382 | Register.\r | |
383 | \r | |
384 | @return The read value from the PCI configuration register.\r | |
385 | \r | |
386 | **/\r | |
387 | UINT16\r | |
388 | EFIAPI\r | |
389 | PciExpressRead16 (\r | |
390 | IN UINTN Address\r | |
391 | );\r | |
392 | \r | |
393 | /**\r | |
394 | Writes a 16-bit PCI configuration register.\r | |
395 | \r | |
396 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
397 | value specified by Value. Value is returned. This function must guarantee\r | |
398 | that all PCI read and write operations are serialized.\r | |
399 | \r | |
400 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
401 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
402 | \r | |
403 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
404 | Register.\r | |
405 | @param Value The value to write.\r | |
406 | \r | |
407 | @return The value written to the PCI configuration register.\r | |
408 | \r | |
409 | **/\r | |
410 | UINT16\r | |
411 | EFIAPI\r | |
412 | PciExpressWrite16 (\r | |
413 | IN UINTN Address,\r | |
414 | IN UINT16 Value\r | |
415 | );\r | |
416 | \r | |
417 | /**\r | |
418 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
419 | a 16-bit value.\r | |
420 | \r | |
421 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
422 | bitwise OR between the read result and the value specified by\r | |
423 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
424 | specified by Address. The value written to the PCI configuration register is\r | |
425 | returned. This function must guarantee that all PCI read and write operations\r | |
426 | are serialized.\r | |
427 | \r | |
428 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
429 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
430 | \r | |
431 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
432 | Register.\r | |
433 | @param OrData The value to OR with the PCI configuration register.\r | |
434 | \r | |
435 | @return The value written back to the PCI configuration register.\r | |
436 | \r | |
437 | **/\r | |
438 | UINT16\r | |
439 | EFIAPI\r | |
440 | PciExpressOr16 (\r | |
441 | IN UINTN Address,\r | |
442 | IN UINT16 OrData\r | |
443 | );\r | |
444 | \r | |
445 | /**\r | |
446 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
447 | value.\r | |
448 | \r | |
449 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
450 | bitwise AND between the read result and the value specified by AndData, and\r | |
451 | writes the result to the 16-bit PCI configuration register specified by\r | |
452 | Address. The value written to the PCI configuration register is returned.\r | |
453 | This function must guarantee that all PCI read and write operations are\r | |
454 | serialized.\r | |
455 | \r | |
456 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
457 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
458 | \r | |
459 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
460 | Register.\r | |
461 | @param AndData The value to AND with the PCI configuration register.\r | |
462 | \r | |
463 | @return The value written back to the PCI configuration register.\r | |
464 | \r | |
465 | **/\r | |
466 | UINT16\r | |
467 | EFIAPI\r | |
468 | PciExpressAnd16 (\r | |
469 | IN UINTN Address,\r | |
470 | IN UINT16 AndData\r | |
471 | );\r | |
472 | \r | |
473 | /**\r | |
474 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
475 | value, followed a bitwise OR with another 16-bit value.\r | |
476 | \r | |
477 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
478 | bitwise AND between the read result and the value specified by AndData,\r | |
479 | performs a bitwise OR between the result of the AND operation and\r | |
480 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
481 | configuration register specified by Address. The value written to the PCI\r | |
482 | configuration register is returned. This function must guarantee that all PCI\r | |
483 | read and write operations are serialized.\r | |
484 | \r | |
485 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
486 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
487 | \r | |
488 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
489 | Register.\r | |
490 | @param AndData The value to AND with the PCI configuration register.\r | |
491 | @param OrData The value to OR with the result of the AND operation.\r | |
492 | \r | |
493 | @return The value written back to the PCI configuration register.\r | |
494 | \r | |
495 | **/\r | |
496 | UINT16\r | |
497 | EFIAPI\r | |
498 | PciExpressAndThenOr16 (\r | |
499 | IN UINTN Address,\r | |
500 | IN UINT16 AndData,\r | |
501 | IN UINT16 OrData\r | |
502 | );\r | |
503 | \r | |
504 | /**\r | |
505 | Reads a bit field of a PCI configuration register.\r | |
506 | \r | |
507 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
508 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
509 | returned.\r | |
510 | \r | |
511 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
512 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
513 | If StartBit is greater than 15, then ASSERT().\r | |
514 | If EndBit is greater than 15, then ASSERT().\r | |
515 | If EndBit is less than StartBit, then ASSERT().\r | |
516 | \r | |
517 | @param Address PCI configuration register to read.\r | |
518 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
519 | Range 0..15.\r | |
520 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
521 | Range 0..15.\r | |
522 | \r | |
523 | @return The value of the bit field read from the PCI configuration register.\r | |
524 | \r | |
525 | **/\r | |
526 | UINT16\r | |
527 | EFIAPI\r | |
528 | PciExpressBitFieldRead16 (\r | |
529 | IN UINTN Address,\r | |
530 | IN UINTN StartBit,\r | |
531 | IN UINTN EndBit\r | |
532 | );\r | |
533 | \r | |
534 | /**\r | |
535 | Writes a bit field to a PCI configuration register.\r | |
536 | \r | |
537 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
538 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
539 | destination PCI configuration register are preserved. The new value of the\r | |
540 | 16-bit register is returned.\r | |
541 | \r | |
542 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
543 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
544 | If StartBit is greater than 15, then ASSERT().\r | |
545 | If EndBit is greater than 15, then ASSERT().\r | |
546 | If EndBit is less than StartBit, then ASSERT().\r | |
547 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
548 | \r | |
549 | @param Address PCI configuration register to write.\r | |
550 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
551 | Range 0..15.\r | |
552 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
553 | Range 0..15.\r | |
554 | @param Value New value of the bit field.\r | |
555 | \r | |
556 | @return The value written back to the PCI configuration register.\r | |
557 | \r | |
558 | **/\r | |
559 | UINT16\r | |
560 | EFIAPI\r | |
561 | PciExpressBitFieldWrite16 (\r | |
562 | IN UINTN Address,\r | |
563 | IN UINTN StartBit,\r | |
564 | IN UINTN EndBit,\r | |
565 | IN UINT16 Value\r | |
566 | );\r | |
567 | \r | |
568 | /**\r | |
569 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
570 | writes the result back to the bit field in the 16-bit port.\r | |
571 | \r | |
572 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
573 | bitwise OR between the read result and the value specified by\r | |
574 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
575 | specified by Address. The value written to the PCI configuration register is\r | |
576 | returned. This function must guarantee that all PCI read and write operations\r | |
577 | are serialized. Extra left bits in OrData are stripped.\r | |
578 | \r | |
579 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
580 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
581 | If StartBit is greater than 15, then ASSERT().\r | |
582 | If EndBit is greater than 15, then ASSERT().\r | |
583 | If EndBit is less than StartBit, then ASSERT().\r | |
584 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
585 | \r | |
586 | @param Address PCI configuration register to write.\r | |
587 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
588 | Range 0..15.\r | |
589 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
590 | Range 0..15.\r | |
591 | @param OrData The value to OR with the PCI configuration register.\r | |
592 | \r | |
593 | @return The value written back to the PCI configuration register.\r | |
594 | \r | |
595 | **/\r | |
596 | UINT16\r | |
597 | EFIAPI\r | |
598 | PciExpressBitFieldOr16 (\r | |
599 | IN UINTN Address,\r | |
600 | IN UINTN StartBit,\r | |
601 | IN UINTN EndBit,\r | |
602 | IN UINT16 OrData\r | |
603 | );\r | |
604 | \r | |
605 | /**\r | |
606 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
607 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
608 | \r | |
609 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
610 | bitwise AND between the read result and the value specified by AndData, and\r | |
611 | writes the result to the 16-bit PCI configuration register specified by\r | |
612 | Address. The value written to the PCI configuration register is returned.\r | |
613 | This function must guarantee that all PCI read and write operations are\r | |
614 | serialized. Extra left bits in AndData are stripped.\r | |
615 | \r | |
616 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
617 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
618 | If StartBit is greater than 15, then ASSERT().\r | |
619 | If EndBit is greater than 15, then ASSERT().\r | |
620 | If EndBit is less than StartBit, then ASSERT().\r | |
621 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
622 | \r | |
623 | @param Address PCI configuration register to write.\r | |
624 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
625 | Range 0..15.\r | |
626 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
627 | Range 0..15.\r | |
628 | @param AndData The value to AND with the PCI configuration register.\r | |
629 | \r | |
630 | @return The value written back to the PCI configuration register.\r | |
631 | \r | |
632 | **/\r | |
633 | UINT16\r | |
634 | EFIAPI\r | |
635 | PciExpressBitFieldAnd16 (\r | |
636 | IN UINTN Address,\r | |
637 | IN UINTN StartBit,\r | |
638 | IN UINTN EndBit,\r | |
639 | IN UINT16 AndData\r | |
640 | );\r | |
641 | \r | |
642 | /**\r | |
643 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
644 | bitwise OR, and writes the result back to the bit field in the\r | |
645 | 16-bit port.\r | |
646 | \r | |
647 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
648 | bitwise AND followed by a bitwise OR between the read result and\r | |
649 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
650 | configuration register specified by Address. The value written to the PCI\r | |
651 | configuration register is returned. This function must guarantee that all PCI\r | |
652 | read and write operations are serialized. Extra left bits in both AndData and\r | |
653 | OrData are stripped.\r | |
654 | \r | |
655 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
656 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
657 | If StartBit is greater than 15, then ASSERT().\r | |
658 | If EndBit is greater than 15, then ASSERT().\r | |
659 | If EndBit is less than StartBit, then ASSERT().\r | |
660 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
661 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
662 | \r | |
663 | @param Address PCI configuration register to write.\r | |
664 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
665 | Range 0..15.\r | |
666 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
667 | Range 0..15.\r | |
668 | @param AndData The value to AND with the PCI configuration register.\r | |
669 | @param OrData The value to OR with the result of the AND operation.\r | |
670 | \r | |
671 | @return The value written back to the PCI configuration register.\r | |
672 | \r | |
673 | **/\r | |
674 | UINT16\r | |
675 | EFIAPI\r | |
676 | PciExpressBitFieldAndThenOr16 (\r | |
677 | IN UINTN Address,\r | |
678 | IN UINTN StartBit,\r | |
679 | IN UINTN EndBit,\r | |
680 | IN UINT16 AndData,\r | |
681 | IN UINT16 OrData\r | |
682 | );\r | |
683 | \r | |
684 | /**\r | |
685 | Reads a 32-bit PCI configuration register.\r | |
686 | \r | |
687 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
688 | This function must guarantee that all PCI read and write operations are\r | |
689 | serialized.\r | |
690 | \r | |
691 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
692 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
693 | \r | |
694 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
695 | Register.\r | |
696 | \r | |
697 | @return The read value from the PCI configuration register.\r | |
698 | \r | |
699 | **/\r | |
700 | UINT32\r | |
701 | EFIAPI\r | |
702 | PciExpressRead32 (\r | |
703 | IN UINTN Address\r | |
704 | );\r | |
705 | \r | |
706 | /**\r | |
707 | Writes a 32-bit PCI configuration register.\r | |
708 | \r | |
709 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
710 | value specified by Value. Value is returned. This function must guarantee\r | |
711 | that all PCI read and write operations are serialized.\r | |
712 | \r | |
713 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
714 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
715 | \r | |
716 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
717 | Register.\r | |
718 | @param Value The value to write.\r | |
719 | \r | |
720 | @return The value written to the PCI configuration register.\r | |
721 | \r | |
722 | **/\r | |
723 | UINT32\r | |
724 | EFIAPI\r | |
725 | PciExpressWrite32 (\r | |
726 | IN UINTN Address,\r | |
727 | IN UINT32 Value\r | |
728 | );\r | |
729 | \r | |
730 | /**\r | |
731 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
732 | a 32-bit value.\r | |
733 | \r | |
734 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
735 | bitwise OR between the read result and the value specified by\r | |
736 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
737 | specified by Address. The value written to the PCI configuration register is\r | |
738 | returned. This function must guarantee that all PCI read and write operations\r | |
739 | are serialized.\r | |
740 | \r | |
741 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
742 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
743 | \r | |
744 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
745 | Register.\r | |
746 | @param OrData The value to OR with the PCI configuration register.\r | |
747 | \r | |
748 | @return The value written back to the PCI configuration register.\r | |
749 | \r | |
750 | **/\r | |
751 | UINT32\r | |
752 | EFIAPI\r | |
753 | PciExpressOr32 (\r | |
754 | IN UINTN Address,\r | |
755 | IN UINT32 OrData\r | |
756 | );\r | |
757 | \r | |
758 | /**\r | |
759 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
760 | value.\r | |
761 | \r | |
762 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
763 | bitwise AND between the read result and the value specified by AndData, and\r | |
764 | writes the result to the 32-bit PCI configuration register specified by\r | |
765 | Address. The value written to the PCI configuration register is returned.\r | |
766 | This function must guarantee that all PCI read and write operations are\r | |
767 | serialized.\r | |
768 | \r | |
769 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
770 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
771 | \r | |
772 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
773 | Register.\r | |
774 | @param AndData The value to AND with the PCI configuration register.\r | |
775 | \r | |
776 | @return The value written back to the PCI configuration register.\r | |
777 | \r | |
778 | **/\r | |
779 | UINT32\r | |
780 | EFIAPI\r | |
781 | PciExpressAnd32 (\r | |
782 | IN UINTN Address,\r | |
783 | IN UINT32 AndData\r | |
784 | );\r | |
785 | \r | |
786 | /**\r | |
787 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
788 | value, followed a bitwise OR with another 32-bit value.\r | |
789 | \r | |
790 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
791 | bitwise AND between the read result and the value specified by AndData,\r | |
792 | performs a bitwise OR between the result of the AND operation and\r | |
793 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
794 | configuration register specified by Address. The value written to the PCI\r | |
795 | configuration register is returned. This function must guarantee that all PCI\r | |
796 | read and write operations are serialized.\r | |
797 | \r | |
798 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
799 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
800 | \r | |
801 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
802 | Register.\r | |
803 | @param AndData The value to AND with the PCI configuration register.\r | |
804 | @param OrData The value to OR with the result of the AND operation.\r | |
805 | \r | |
806 | @return The value written back to the PCI configuration register.\r | |
807 | \r | |
808 | **/\r | |
809 | UINT32\r | |
810 | EFIAPI\r | |
811 | PciExpressAndThenOr32 (\r | |
812 | IN UINTN Address,\r | |
813 | IN UINT32 AndData,\r | |
814 | IN UINT32 OrData\r | |
815 | );\r | |
816 | \r | |
817 | /**\r | |
818 | Reads a bit field of a PCI configuration register.\r | |
819 | \r | |
820 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
821 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
822 | returned.\r | |
823 | \r | |
824 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
825 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
826 | If StartBit is greater than 31, then ASSERT().\r | |
827 | If EndBit is greater than 31, then ASSERT().\r | |
828 | If EndBit is less than StartBit, then ASSERT().\r | |
829 | \r | |
830 | @param Address PCI configuration register to read.\r | |
831 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
832 | Range 0..31.\r | |
833 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
834 | Range 0..31.\r | |
835 | \r | |
836 | @return The value of the bit field read from the PCI configuration register.\r | |
837 | \r | |
838 | **/\r | |
839 | UINT32\r | |
840 | EFIAPI\r | |
841 | PciExpressBitFieldRead32 (\r | |
842 | IN UINTN Address,\r | |
843 | IN UINTN StartBit,\r | |
844 | IN UINTN EndBit\r | |
845 | );\r | |
846 | \r | |
847 | /**\r | |
848 | Writes a bit field to a PCI configuration register.\r | |
849 | \r | |
850 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
851 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
852 | destination PCI configuration register are preserved. The new value of the\r | |
853 | 32-bit register is returned.\r | |
854 | \r | |
855 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
856 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
857 | If StartBit is greater than 31, then ASSERT().\r | |
858 | If EndBit is greater than 31, then ASSERT().\r | |
859 | If EndBit is less than StartBit, then ASSERT().\r | |
860 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
861 | \r | |
862 | @param Address PCI configuration register to write.\r | |
863 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
864 | Range 0..31.\r | |
865 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
866 | Range 0..31.\r | |
867 | @param Value New value of the bit field.\r | |
868 | \r | |
869 | @return The value written back to the PCI configuration register.\r | |
870 | \r | |
871 | **/\r | |
872 | UINT32\r | |
873 | EFIAPI\r | |
874 | PciExpressBitFieldWrite32 (\r | |
875 | IN UINTN Address,\r | |
876 | IN UINTN StartBit,\r | |
877 | IN UINTN EndBit,\r | |
878 | IN UINT32 Value\r | |
879 | );\r | |
880 | \r | |
881 | /**\r | |
882 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
883 | writes the result back to the bit field in the 32-bit port.\r | |
884 | \r | |
885 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
886 | bitwise OR between the read result and the value specified by\r | |
887 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
888 | specified by Address. The value written to the PCI configuration register is\r | |
889 | returned. This function must guarantee that all PCI read and write operations\r | |
890 | are serialized. Extra left bits in OrData are stripped.\r | |
891 | \r | |
892 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
893 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
894 | If StartBit is greater than 31, then ASSERT().\r | |
895 | If EndBit is greater than 31, then ASSERT().\r | |
896 | If EndBit is less than StartBit, then ASSERT().\r | |
897 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
898 | \r | |
899 | @param Address PCI configuration register to write.\r | |
900 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
901 | Range 0..31.\r | |
902 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
903 | Range 0..31.\r | |
904 | @param OrData The value to OR with the PCI configuration register.\r | |
905 | \r | |
906 | @return The value written back to the PCI configuration register.\r | |
907 | \r | |
908 | **/\r | |
909 | UINT32\r | |
910 | EFIAPI\r | |
911 | PciExpressBitFieldOr32 (\r | |
912 | IN UINTN Address,\r | |
913 | IN UINTN StartBit,\r | |
914 | IN UINTN EndBit,\r | |
915 | IN UINT32 OrData\r | |
916 | );\r | |
917 | \r | |
918 | /**\r | |
919 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
920 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
921 | \r | |
922 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
923 | bitwise AND between the read result and the value specified by AndData, and\r | |
924 | writes the result to the 32-bit PCI configuration register specified by\r | |
925 | Address. The value written to the PCI configuration register is returned.\r | |
926 | This function must guarantee that all PCI read and write operations are\r | |
927 | serialized. Extra left bits in AndData are stripped.\r | |
928 | \r | |
929 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
930 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
931 | If StartBit is greater than 31, then ASSERT().\r | |
932 | If EndBit is greater than 31, then ASSERT().\r | |
933 | If EndBit is less than StartBit, then ASSERT().\r | |
934 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
935 | \r | |
936 | @param Address PCI configuration register to write.\r | |
937 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
938 | Range 0..31.\r | |
939 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
940 | Range 0..31.\r | |
941 | @param AndData The value to AND with the PCI configuration register.\r | |
942 | \r | |
943 | @return The value written back to the PCI configuration register.\r | |
944 | \r | |
945 | **/\r | |
946 | UINT32\r | |
947 | EFIAPI\r | |
948 | PciExpressBitFieldAnd32 (\r | |
949 | IN UINTN Address,\r | |
950 | IN UINTN StartBit,\r | |
951 | IN UINTN EndBit,\r | |
952 | IN UINT32 AndData\r | |
953 | );\r | |
954 | \r | |
955 | /**\r | |
956 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
957 | bitwise OR, and writes the result back to the bit field in the\r | |
958 | 32-bit port.\r | |
959 | \r | |
960 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
961 | bitwise AND followed by a bitwise OR between the read result and\r | |
962 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
963 | configuration register specified by Address. The value written to the PCI\r | |
964 | configuration register is returned. This function must guarantee that all PCI\r | |
965 | read and write operations are serialized. Extra left bits in both AndData and\r | |
966 | OrData are stripped.\r | |
967 | \r | |
968 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
969 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
970 | If StartBit is greater than 31, then ASSERT().\r | |
971 | If EndBit is greater than 31, then ASSERT().\r | |
972 | If EndBit is less than StartBit, then ASSERT().\r | |
973 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
974 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
975 | \r | |
976 | @param Address PCI configuration register to write.\r | |
977 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
978 | Range 0..31.\r | |
979 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
980 | Range 0..31.\r | |
981 | @param AndData The value to AND with the PCI configuration register.\r | |
982 | @param OrData The value to OR with the result of the AND operation.\r | |
983 | \r | |
984 | @return The value written back to the PCI configuration register.\r | |
985 | \r | |
986 | **/\r | |
987 | UINT32\r | |
988 | EFIAPI\r | |
989 | PciExpressBitFieldAndThenOr32 (\r | |
990 | IN UINTN Address,\r | |
991 | IN UINTN StartBit,\r | |
992 | IN UINTN EndBit,\r | |
993 | IN UINT32 AndData,\r | |
994 | IN UINT32 OrData\r | |
995 | );\r | |
996 | \r | |
997 | /**\r | |
998 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
999 | \r | |
1000 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1001 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1002 | configuration registers from a single PCI function to be read. Size is\r | |
1003 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1004 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1005 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1006 | end of the range.\r | |
1007 | \r | |
1008 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1009 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1010 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1011 | \r | |
1012 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1013 | Function and Register.\r | |
1014 | @param Size Size in bytes of the transfer.\r | |
1015 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1016 | \r | |
1017 | @return Size read data from StartAddress.\r | |
1018 | \r | |
1019 | **/\r | |
1020 | UINTN\r | |
1021 | EFIAPI\r | |
1022 | PciExpressReadBuffer (\r | |
1023 | IN UINTN StartAddress,\r | |
1024 | IN UINTN Size,\r | |
1025 | OUT VOID *Buffer\r | |
1026 | );\r | |
1027 | \r | |
1028 | /**\r | |
1029 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1030 | configuration space.\r | |
1031 | \r | |
1032 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1033 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1034 | configuration registers from a single PCI function to be written. Size is\r | |
1035 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1036 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1037 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1038 | and the end of the range.\r | |
1039 | \r | |
1040 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1041 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1042 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1043 | \r | |
1044 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1045 | Function and Register.\r | |
1046 | @param Size Size in bytes of the transfer.\r | |
1047 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1048 | \r | |
1049 | @return Size written to StartAddress.\r | |
1050 | \r | |
1051 | **/\r | |
1052 | UINTN\r | |
1053 | EFIAPI\r | |
1054 | PciExpressWriteBuffer (\r | |
1055 | IN UINTN StartAddress,\r | |
1056 | IN UINTN Size,\r | |
1057 | IN VOID *Buffer\r | |
1058 | );\r | |
1059 | \r | |
1060 | #endif\r |