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2 Provides services to access PCI Configuration Space using the MMIO PCI Express window.
4 This library is identical to the PCI Library, except the access method for performing PCI
5 configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
6 is defined by PcdPciExpressBaseAddress.
8 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #ifndef __PCI_EXPRESS_LIB_H__
20 #define __PCI_EXPRESS_LIB_H__
23 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
24 address that can be passed to the PCI Library functions.
26 Computes an address that is compatible with the PCI Library functions. The
27 unused upper bits of Bus, Device, Function and Register are stripped prior to
28 the generation of the address.
30 @param Bus PCI Bus number. Range 0..255.
31 @param Device PCI Device number. Range 0..31.
32 @param Function PCI Function number. Range 0..7.
33 @param Register PCI Register number. Range 0..4095.
35 @return The encode PCI address.
38 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))
41 Registers a PCI device so PCI configuration registers may be accessed after
42 SetVirtualAddressMap().
44 Registers the PCI device specified by Address so all the PCI configuration
45 registers associated with that PCI device may be accessed after SetVirtualAddressMap()
48 If Address > 0x0FFFFFFF, then ASSERT().
50 @param Address Address that encodes the PCI Bus, Device, Function and
53 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
54 @retval RETURN_UNSUPPORTED An attempt was made to call this function
55 after ExitBootServices().
56 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
57 at runtime could not be mapped.
58 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
59 complete the registration.
64 PciExpressRegisterForRuntimeAccess (
69 Reads an 8-bit PCI configuration register.
71 Reads and returns the 8-bit PCI configuration register specified by Address.
72 This function must guarantee that all PCI read and write operations are
75 If Address > 0x0FFFFFFF, then ASSERT().
77 @param Address Address that encodes the PCI Bus, Device, Function and
80 @return The read value from the PCI configuration register.
90 Writes an 8-bit PCI configuration register.
92 Writes the 8-bit PCI configuration register specified by Address with the
93 value specified by Value. Value is returned. This function must guarantee
94 that all PCI read and write operations are serialized.
96 If Address > 0x0FFFFFFF, then ASSERT().
98 @param Address Address that encodes the PCI Bus, Device, Function and
100 @param Value The value to write.
102 @return The value written to the PCI configuration register.
113 Performs a bitwise OR of an 8-bit PCI configuration register with
116 Reads the 8-bit PCI configuration register specified by Address, performs a
117 bitwise OR between the read result and the value specified by
118 OrData, and writes the result to the 8-bit PCI configuration register
119 specified by Address. The value written to the PCI configuration register is
120 returned. This function must guarantee that all PCI read and write operations
123 If Address > 0x0FFFFFFF, then ASSERT().
125 @param Address Address that encodes the PCI Bus, Device, Function and
127 @param OrData The value to OR with the PCI configuration register.
129 @return The value written back to the PCI configuration register.
140 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
143 Reads the 8-bit PCI configuration register specified by Address, performs a
144 bitwise AND between the read result and the value specified by AndData, and
145 writes the result to the 8-bit PCI configuration register specified by
146 Address. The value written to the PCI configuration register is returned.
147 This function must guarantee that all PCI read and write operations are
150 If Address > 0x0FFFFFFF, then ASSERT().
152 @param Address Address that encodes the PCI Bus, Device, Function and
154 @param AndData The value to AND with the PCI configuration register.
156 @return The value written back to the PCI configuration register.
167 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
168 value, followed a bitwise OR with another 8-bit value.
170 Reads the 8-bit PCI configuration register specified by Address, performs a
171 bitwise AND between the read result and the value specified by AndData,
172 performs a bitwise OR between the result of the AND operation and
173 the value specified by OrData, and writes the result to the 8-bit PCI
174 configuration register specified by Address. The value written to the PCI
175 configuration register is returned. This function must guarantee that all PCI
176 read and write operations are serialized.
178 If Address > 0x0FFFFFFF, then ASSERT().
180 @param Address Address that encodes the PCI Bus, Device, Function and
182 @param AndData The value to AND with the PCI configuration register.
183 @param OrData The value to OR with the result of the AND operation.
185 @return The value written back to the PCI configuration register.
190 PciExpressAndThenOr8 (
197 Reads a bit field of a PCI configuration register.
199 Reads the bit field in an 8-bit PCI configuration register. The bit field is
200 specified by the StartBit and the EndBit. The value of the bit field is
203 If Address > 0x0FFFFFFF, then ASSERT().
204 If StartBit is greater than 7, then ASSERT().
205 If EndBit is greater than 7, then ASSERT().
206 If EndBit is less than StartBit, then ASSERT().
208 @param Address PCI configuration register to read.
209 @param StartBit The ordinal of the least significant bit in the bit field.
211 @param EndBit The ordinal of the most significant bit in the bit field.
214 @return The value of the bit field read from the PCI configuration register.
219 PciExpressBitFieldRead8 (
226 Writes a bit field to a PCI configuration register.
228 Writes Value to the bit field of the PCI configuration register. The bit
229 field is specified by the StartBit and the EndBit. All other bits in the
230 destination PCI configuration register are preserved. The new value of the
231 8-bit register is returned.
233 If Address > 0x0FFFFFFF, then ASSERT().
234 If StartBit is greater than 7, then ASSERT().
235 If EndBit is greater than 7, then ASSERT().
236 If EndBit is less than StartBit, then ASSERT().
237 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
239 @param Address PCI configuration register to write.
240 @param StartBit The ordinal of the least significant bit in the bit field.
242 @param EndBit The ordinal of the most significant bit in the bit field.
244 @param Value New value of the bit field.
246 @return The value written back to the PCI configuration register.
251 PciExpressBitFieldWrite8 (
259 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
260 writes the result back to the bit field in the 8-bit port.
262 Reads the 8-bit PCI configuration register specified by Address, performs a
263 bitwise OR between the read result and the value specified by
264 OrData, and writes the result to the 8-bit PCI configuration register
265 specified by Address. The value written to the PCI configuration register is
266 returned. This function must guarantee that all PCI read and write operations
267 are serialized. Extra left bits in OrData are stripped.
269 If Address > 0x0FFFFFFF, then ASSERT().
270 If StartBit is greater than 7, then ASSERT().
271 If EndBit is greater than 7, then ASSERT().
272 If EndBit is less than StartBit, then ASSERT().
273 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
275 @param Address PCI configuration register to write.
276 @param StartBit The ordinal of the least significant bit in the bit field.
278 @param EndBit The ordinal of the most significant bit in the bit field.
280 @param OrData The value to OR with the PCI configuration register.
282 @return The value written back to the PCI configuration register.
287 PciExpressBitFieldOr8 (
295 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
296 AND, and writes the result back to the bit field in the 8-bit register.
298 Reads the 8-bit PCI configuration register specified by Address, performs a
299 bitwise AND between the read result and the value specified by AndData, and
300 writes the result to the 8-bit PCI configuration register specified by
301 Address. The value written to the PCI configuration register is returned.
302 This function must guarantee that all PCI read and write operations are
303 serialized. Extra left bits in AndData are stripped.
305 If Address > 0x0FFFFFFF, then ASSERT().
306 If StartBit is greater than 7, then ASSERT().
307 If EndBit is greater than 7, then ASSERT().
308 If EndBit is less than StartBit, then ASSERT().
309 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
311 @param Address PCI configuration register to write.
312 @param StartBit The ordinal of the least significant bit in the bit field.
314 @param EndBit The ordinal of the most significant bit in the bit field.
316 @param AndData The value to AND with the PCI configuration register.
318 @return The value written back to the PCI configuration register.
323 PciExpressBitFieldAnd8 (
331 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
332 bitwise OR, and writes the result back to the bit field in the
335 Reads the 8-bit PCI configuration register specified by Address, performs a
336 bitwise AND followed by a bitwise OR between the read result and
337 the value specified by AndData, and writes the result to the 8-bit PCI
338 configuration register specified by Address. The value written to the PCI
339 configuration register is returned. This function must guarantee that all PCI
340 read and write operations are serialized. Extra left bits in both AndData and
343 If Address > 0x0FFFFFFF, then ASSERT().
344 If StartBit is greater than 7, then ASSERT().
345 If EndBit is greater than 7, then ASSERT().
346 If EndBit is less than StartBit, then ASSERT().
347 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
348 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
350 @param Address PCI configuration register to write.
351 @param StartBit The ordinal of the least significant bit in the bit field.
353 @param EndBit The ordinal of the most significant bit in the bit field.
355 @param AndData The value to AND with the PCI configuration register.
356 @param OrData The value to OR with the result of the AND operation.
358 @return The value written back to the PCI configuration register.
363 PciExpressBitFieldAndThenOr8 (
372 Reads a 16-bit PCI configuration register.
374 Reads and returns the 16-bit PCI configuration register specified by Address.
375 This function must guarantee that all PCI read and write operations are
378 If Address > 0x0FFFFFFF, then ASSERT().
379 If Address is not aligned on a 16-bit boundary, then ASSERT().
381 @param Address Address that encodes the PCI Bus, Device, Function and
384 @return The read value from the PCI configuration register.
394 Writes a 16-bit PCI configuration register.
396 Writes the 16-bit PCI configuration register specified by Address with the
397 value specified by Value. Value is returned. This function must guarantee
398 that all PCI read and write operations are serialized.
400 If Address > 0x0FFFFFFF, then ASSERT().
401 If Address is not aligned on a 16-bit boundary, then ASSERT().
403 @param Address Address that encodes the PCI Bus, Device, Function and
405 @param Value The value to write.
407 @return The value written to the PCI configuration register.
418 Performs a bitwise OR of a 16-bit PCI configuration register with
421 Reads the 16-bit PCI configuration register specified by Address, performs a
422 bitwise OR between the read result and the value specified by
423 OrData, and writes the result to the 16-bit PCI configuration register
424 specified by Address. The value written to the PCI configuration register is
425 returned. This function must guarantee that all PCI read and write operations
428 If Address > 0x0FFFFFFF, then ASSERT().
429 If Address is not aligned on a 16-bit boundary, then ASSERT().
431 @param Address Address that encodes the PCI Bus, Device, Function and
433 @param OrData The value to OR with the PCI configuration register.
435 @return The value written back to the PCI configuration register.
446 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
449 Reads the 16-bit PCI configuration register specified by Address, performs a
450 bitwise AND between the read result and the value specified by AndData, and
451 writes the result to the 16-bit PCI configuration register specified by
452 Address. The value written to the PCI configuration register is returned.
453 This function must guarantee that all PCI read and write operations are
456 If Address > 0x0FFFFFFF, then ASSERT().
457 If Address is not aligned on a 16-bit boundary, then ASSERT().
459 @param Address Address that encodes the PCI Bus, Device, Function and
461 @param AndData The value to AND with the PCI configuration register.
463 @return The value written back to the PCI configuration register.
474 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
475 value, followed a bitwise OR with another 16-bit value.
477 Reads the 16-bit PCI configuration register specified by Address, performs a
478 bitwise AND between the read result and the value specified by AndData,
479 performs a bitwise OR between the result of the AND operation and
480 the value specified by OrData, and writes the result to the 16-bit PCI
481 configuration register specified by Address. The value written to the PCI
482 configuration register is returned. This function must guarantee that all PCI
483 read and write operations are serialized.
485 If Address > 0x0FFFFFFF, then ASSERT().
486 If Address is not aligned on a 16-bit boundary, then ASSERT().
488 @param Address Address that encodes the PCI Bus, Device, Function and
490 @param AndData The value to AND with the PCI configuration register.
491 @param OrData The value to OR with the result of the AND operation.
493 @return The value written back to the PCI configuration register.
498 PciExpressAndThenOr16 (
505 Reads a bit field of a PCI configuration register.
507 Reads the bit field in a 16-bit PCI configuration register. The bit field is
508 specified by the StartBit and the EndBit. The value of the bit field is
511 If Address > 0x0FFFFFFF, then ASSERT().
512 If Address is not aligned on a 16-bit boundary, then ASSERT().
513 If StartBit is greater than 15, then ASSERT().
514 If EndBit is greater than 15, then ASSERT().
515 If EndBit is less than StartBit, then ASSERT().
517 @param Address PCI configuration register to read.
518 @param StartBit The ordinal of the least significant bit in the bit field.
520 @param EndBit The ordinal of the most significant bit in the bit field.
523 @return The value of the bit field read from the PCI configuration register.
528 PciExpressBitFieldRead16 (
535 Writes a bit field to a PCI configuration register.
537 Writes Value to the bit field of the PCI configuration register. The bit
538 field is specified by the StartBit and the EndBit. All other bits in the
539 destination PCI configuration register are preserved. The new value of the
540 16-bit register is returned.
542 If Address > 0x0FFFFFFF, then ASSERT().
543 If Address is not aligned on a 16-bit boundary, then ASSERT().
544 If StartBit is greater than 15, then ASSERT().
545 If EndBit is greater than 15, then ASSERT().
546 If EndBit is less than StartBit, then ASSERT().
547 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
549 @param Address PCI configuration register to write.
550 @param StartBit The ordinal of the least significant bit in the bit field.
552 @param EndBit The ordinal of the most significant bit in the bit field.
554 @param Value New value of the bit field.
556 @return The value written back to the PCI configuration register.
561 PciExpressBitFieldWrite16 (
569 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
570 writes the result back to the bit field in the 16-bit port.
572 Reads the 16-bit PCI configuration register specified by Address, performs a
573 bitwise OR between the read result and the value specified by
574 OrData, and writes the result to the 16-bit PCI configuration register
575 specified by Address. The value written to the PCI configuration register is
576 returned. This function must guarantee that all PCI read and write operations
577 are serialized. Extra left bits in OrData are stripped.
579 If Address > 0x0FFFFFFF, then ASSERT().
580 If Address is not aligned on a 16-bit boundary, then ASSERT().
581 If StartBit is greater than 15, then ASSERT().
582 If EndBit is greater than 15, then ASSERT().
583 If EndBit is less than StartBit, then ASSERT().
584 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
586 @param Address PCI configuration register to write.
587 @param StartBit The ordinal of the least significant bit in the bit field.
589 @param EndBit The ordinal of the most significant bit in the bit field.
591 @param OrData The value to OR with the PCI configuration register.
593 @return The value written back to the PCI configuration register.
598 PciExpressBitFieldOr16 (
606 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
607 AND, and writes the result back to the bit field in the 16-bit register.
609 Reads the 16-bit PCI configuration register specified by Address, performs a
610 bitwise AND between the read result and the value specified by AndData, and
611 writes the result to the 16-bit PCI configuration register specified by
612 Address. The value written to the PCI configuration register is returned.
613 This function must guarantee that all PCI read and write operations are
614 serialized. Extra left bits in AndData are stripped.
616 If Address > 0x0FFFFFFF, then ASSERT().
617 If Address is not aligned on a 16-bit boundary, then ASSERT().
618 If StartBit is greater than 15, then ASSERT().
619 If EndBit is greater than 15, then ASSERT().
620 If EndBit is less than StartBit, then ASSERT().
621 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
623 @param Address PCI configuration register to write.
624 @param StartBit The ordinal of the least significant bit in the bit field.
626 @param EndBit The ordinal of the most significant bit in the bit field.
628 @param AndData The value to AND with the PCI configuration register.
630 @return The value written back to the PCI configuration register.
635 PciExpressBitFieldAnd16 (
643 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
644 bitwise OR, and writes the result back to the bit field in the
647 Reads the 16-bit PCI configuration register specified by Address, performs a
648 bitwise AND followed by a bitwise OR between the read result and
649 the value specified by AndData, and writes the result to the 16-bit PCI
650 configuration register specified by Address. The value written to the PCI
651 configuration register is returned. This function must guarantee that all PCI
652 read and write operations are serialized. Extra left bits in both AndData and
655 If Address > 0x0FFFFFFF, then ASSERT().
656 If Address is not aligned on a 16-bit boundary, then ASSERT().
657 If StartBit is greater than 15, then ASSERT().
658 If EndBit is greater than 15, then ASSERT().
659 If EndBit is less than StartBit, then ASSERT().
660 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
661 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
663 @param Address PCI configuration register to write.
664 @param StartBit The ordinal of the least significant bit in the bit field.
666 @param EndBit The ordinal of the most significant bit in the bit field.
668 @param AndData The value to AND with the PCI configuration register.
669 @param OrData The value to OR with the result of the AND operation.
671 @return The value written back to the PCI configuration register.
676 PciExpressBitFieldAndThenOr16 (
685 Reads a 32-bit PCI configuration register.
687 Reads and returns the 32-bit PCI configuration register specified by Address.
688 This function must guarantee that all PCI read and write operations are
691 If Address > 0x0FFFFFFF, then ASSERT().
692 If Address is not aligned on a 32-bit boundary, then ASSERT().
694 @param Address Address that encodes the PCI Bus, Device, Function and
697 @return The read value from the PCI configuration register.
707 Writes a 32-bit PCI configuration register.
709 Writes the 32-bit PCI configuration register specified by Address with the
710 value specified by Value. Value is returned. This function must guarantee
711 that all PCI read and write operations are serialized.
713 If Address > 0x0FFFFFFF, then ASSERT().
714 If Address is not aligned on a 32-bit boundary, then ASSERT().
716 @param Address Address that encodes the PCI Bus, Device, Function and
718 @param Value The value to write.
720 @return The value written to the PCI configuration register.
731 Performs a bitwise OR of a 32-bit PCI configuration register with
734 Reads the 32-bit PCI configuration register specified by Address, performs a
735 bitwise OR between the read result and the value specified by
736 OrData, and writes the result to the 32-bit PCI configuration register
737 specified by Address. The value written to the PCI configuration register is
738 returned. This function must guarantee that all PCI read and write operations
741 If Address > 0x0FFFFFFF, then ASSERT().
742 If Address is not aligned on a 32-bit boundary, then ASSERT().
744 @param Address Address that encodes the PCI Bus, Device, Function and
746 @param OrData The value to OR with the PCI configuration register.
748 @return The value written back to the PCI configuration register.
759 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
762 Reads the 32-bit PCI configuration register specified by Address, performs a
763 bitwise AND between the read result and the value specified by AndData, and
764 writes the result to the 32-bit PCI configuration register specified by
765 Address. The value written to the PCI configuration register is returned.
766 This function must guarantee that all PCI read and write operations are
769 If Address > 0x0FFFFFFF, then ASSERT().
770 If Address is not aligned on a 32-bit boundary, then ASSERT().
772 @param Address Address that encodes the PCI Bus, Device, Function and
774 @param AndData The value to AND with the PCI configuration register.
776 @return The value written back to the PCI configuration register.
787 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
788 value, followed a bitwise OR with another 32-bit value.
790 Reads the 32-bit PCI configuration register specified by Address, performs a
791 bitwise AND between the read result and the value specified by AndData,
792 performs a bitwise OR between the result of the AND operation and
793 the value specified by OrData, and writes the result to the 32-bit PCI
794 configuration register specified by Address. The value written to the PCI
795 configuration register is returned. This function must guarantee that all PCI
796 read and write operations are serialized.
798 If Address > 0x0FFFFFFF, then ASSERT().
799 If Address is not aligned on a 32-bit boundary, then ASSERT().
801 @param Address Address that encodes the PCI Bus, Device, Function and
803 @param AndData The value to AND with the PCI configuration register.
804 @param OrData The value to OR with the result of the AND operation.
806 @return The value written back to the PCI configuration register.
811 PciExpressAndThenOr32 (
818 Reads a bit field of a PCI configuration register.
820 Reads the bit field in a 32-bit PCI configuration register. The bit field is
821 specified by the StartBit and the EndBit. The value of the bit field is
824 If Address > 0x0FFFFFFF, then ASSERT().
825 If Address is not aligned on a 32-bit boundary, then ASSERT().
826 If StartBit is greater than 31, then ASSERT().
827 If EndBit is greater than 31, then ASSERT().
828 If EndBit is less than StartBit, then ASSERT().
830 @param Address PCI configuration register to read.
831 @param StartBit The ordinal of the least significant bit in the bit field.
833 @param EndBit The ordinal of the most significant bit in the bit field.
836 @return The value of the bit field read from the PCI configuration register.
841 PciExpressBitFieldRead32 (
848 Writes a bit field to a PCI configuration register.
850 Writes Value to the bit field of the PCI configuration register. The bit
851 field is specified by the StartBit and the EndBit. All other bits in the
852 destination PCI configuration register are preserved. The new value of the
853 32-bit register is returned.
855 If Address > 0x0FFFFFFF, then ASSERT().
856 If Address is not aligned on a 32-bit boundary, then ASSERT().
857 If StartBit is greater than 31, then ASSERT().
858 If EndBit is greater than 31, then ASSERT().
859 If EndBit is less than StartBit, then ASSERT().
860 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
862 @param Address PCI configuration register to write.
863 @param StartBit The ordinal of the least significant bit in the bit field.
865 @param EndBit The ordinal of the most significant bit in the bit field.
867 @param Value New value of the bit field.
869 @return The value written back to the PCI configuration register.
874 PciExpressBitFieldWrite32 (
882 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
883 writes the result back to the bit field in the 32-bit port.
885 Reads the 32-bit PCI configuration register specified by Address, performs a
886 bitwise OR between the read result and the value specified by
887 OrData, and writes the result to the 32-bit PCI configuration register
888 specified by Address. The value written to the PCI configuration register is
889 returned. This function must guarantee that all PCI read and write operations
890 are serialized. Extra left bits in OrData are stripped.
892 If Address > 0x0FFFFFFF, then ASSERT().
893 If Address is not aligned on a 32-bit boundary, then ASSERT().
894 If StartBit is greater than 31, then ASSERT().
895 If EndBit is greater than 31, then ASSERT().
896 If EndBit is less than StartBit, then ASSERT().
897 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
899 @param Address PCI configuration register to write.
900 @param StartBit The ordinal of the least significant bit in the bit field.
902 @param EndBit The ordinal of the most significant bit in the bit field.
904 @param OrData The value to OR with the PCI configuration register.
906 @return The value written back to the PCI configuration register.
911 PciExpressBitFieldOr32 (
919 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
920 AND, and writes the result back to the bit field in the 32-bit register.
922 Reads the 32-bit PCI configuration register specified by Address, performs a
923 bitwise AND between the read result and the value specified by AndData, and
924 writes the result to the 32-bit PCI configuration register specified by
925 Address. The value written to the PCI configuration register is returned.
926 This function must guarantee that all PCI read and write operations are
927 serialized. Extra left bits in AndData are stripped.
929 If Address > 0x0FFFFFFF, then ASSERT().
930 If Address is not aligned on a 32-bit boundary, then ASSERT().
931 If StartBit is greater than 31, then ASSERT().
932 If EndBit is greater than 31, then ASSERT().
933 If EndBit is less than StartBit, then ASSERT().
934 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
936 @param Address PCI configuration register to write.
937 @param StartBit The ordinal of the least significant bit in the bit field.
939 @param EndBit The ordinal of the most significant bit in the bit field.
941 @param AndData The value to AND with the PCI configuration register.
943 @return The value written back to the PCI configuration register.
948 PciExpressBitFieldAnd32 (
956 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
957 bitwise OR, and writes the result back to the bit field in the
960 Reads the 32-bit PCI configuration register specified by Address, performs a
961 bitwise AND followed by a bitwise OR between the read result and
962 the value specified by AndData, and writes the result to the 32-bit PCI
963 configuration register specified by Address. The value written to the PCI
964 configuration register is returned. This function must guarantee that all PCI
965 read and write operations are serialized. Extra left bits in both AndData and
968 If Address > 0x0FFFFFFF, then ASSERT().
969 If Address is not aligned on a 32-bit boundary, then ASSERT().
970 If StartBit is greater than 31, then ASSERT().
971 If EndBit is greater than 31, then ASSERT().
972 If EndBit is less than StartBit, then ASSERT().
973 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
974 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
976 @param Address PCI configuration register to write.
977 @param StartBit The ordinal of the least significant bit in the bit field.
979 @param EndBit The ordinal of the most significant bit in the bit field.
981 @param AndData The value to AND with the PCI configuration register.
982 @param OrData The value to OR with the result of the AND operation.
984 @return The value written back to the PCI configuration register.
989 PciExpressBitFieldAndThenOr32 (
998 Reads a range of PCI configuration registers into a caller supplied buffer.
1000 Reads the range of PCI configuration registers specified by StartAddress and
1001 Size into the buffer specified by Buffer. This function only allows the PCI
1002 configuration registers from a single PCI function to be read. Size is
1003 returned. When possible 32-bit PCI configuration read cycles are used to read
1004 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1005 and 16-bit PCI configuration read cycles may be used at the beginning and the
1008 If StartAddress > 0x0FFFFFFF, then ASSERT().
1009 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1010 If Size > 0 and Buffer is NULL, then ASSERT().
1012 @param StartAddress Starting address that encodes the PCI Bus, Device,
1013 Function and Register.
1014 @param Size Size in bytes of the transfer.
1015 @param Buffer Pointer to a buffer receiving the data read.
1017 @return Size read data from StartAddress.
1022 PciExpressReadBuffer (
1023 IN UINTN StartAddress
,
1029 Copies the data in a caller supplied buffer to a specified range of PCI
1030 configuration space.
1032 Writes the range of PCI configuration registers specified by StartAddress and
1033 Size from the buffer specified by Buffer. This function only allows the PCI
1034 configuration registers from a single PCI function to be written. Size is
1035 returned. When possible 32-bit PCI configuration write cycles are used to
1036 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1037 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1038 and the end of the range.
1040 If StartAddress > 0x0FFFFFFF, then ASSERT().
1041 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1042 If Size > 0 and Buffer is NULL, then ASSERT().
1044 @param StartAddress Starting address that encodes the PCI Bus, Device,
1045 Function and Register.
1046 @param Size Size in bytes of the transfer.
1047 @param Buffer Pointer to a buffer containing the data to write.
1049 @return Size written to StartAddress.
1054 PciExpressWriteBuffer (
1055 IN UINTN StartAddress
,