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1/** @file\r
2 Definitions for network adapter card.\r
3\r
4Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>\r
5SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
7**/\r
8\r
9#ifndef _E100B_H_\r
10#define _E100B_H_\r
11\r
12// pci config offsets:\r
13\r
14#define RX_BUFFER_COUNT 32\r
15#define TX_BUFFER_COUNT 32\r
16\r
17#define PCI_VENDOR_ID_INTEL 0x8086\r
18#define PCI_DEVICE_ID_INTEL_82557 0x1229\r
19#define D100_VENDOR_ID 0x8086\r
20#define D100_DEVICE_ID 0x1229\r
21#define D102_DEVICE_ID 0x2449\r
22\r
23#define ICH3_DEVICE_ID_1 0x1031\r
24#define ICH3_DEVICE_ID_2 0x1032\r
25#define ICH3_DEVICE_ID_3 0x1033\r
26#define ICH3_DEVICE_ID_4 0x1034\r
27#define ICH3_DEVICE_ID_5 0x1035\r
28#define ICH3_DEVICE_ID_6 0x1036\r
29#define ICH3_DEVICE_ID_7 0x1037\r
30#define ICH3_DEVICE_ID_8 0x1038\r
31\r
32#define SPEEDO_DEVICE_ID 0x1227\r
33#define SPLASH1_DEVICE_ID 0x1226\r
34\r
35\r
36// bit fields for the command\r
37#define PCI_COMMAND_MASTER 0x04 // bit 2\r
38#define PCI_COMMAND_IO 0x01 // bit 0\r
39#define PCI_COMMAND 0x04\r
40#define PCI_LATENCY_TIMER 0x0D\r
41\r
42#define ETHER_MAC_ADDR_LEN 6\r
43#ifdef AVL_XXX\r
44#define ETHER_HEADER_LEN 14\r
45// media interface type\r
46// #define INTERFACE_TYPE "\r
47\r
48// Hardware type values\r
49#define HW_ETHER_TYPE 1\r
50#define HW_EXPERIMENTAL_ETHER_TYPE 2\r
51#define HW_IEEE_TYPE 6\r
52#define HW_ARCNET_TYPE 7\r
53\r
54#endif // AVL_XXX\r
55\r
56#define MAX_ETHERNET_PKT_SIZE 1514 // including eth header\r
57#define RX_BUFFER_SIZE 1536 // including crc and padding\r
58#define TX_BUFFER_SIZE 64\r
59#define ETH_MTU 1500 // does not include ethernet header length\r
60\r
61#define SPEEDO3_TOTAL_SIZE 0x20\r
62\r
63#pragma pack(1)\r
64\r
65typedef struct eth {\r
66 UINT8 dest_addr[PXE_HWADDR_LEN_ETHER];\r
67 UINT8 src_addr[PXE_HWADDR_LEN_ETHER];\r
68 UINT16 type;\r
69} EtherHeader;\r
70\r
71#pragma pack(1)\r
72typedef struct CONFIG_HEADER {\r
73 UINT16 VendorID;\r
74 UINT16 DeviceID;\r
75 UINT16 Command;\r
76 UINT16 Status;\r
77 UINT16 RevID;\r
78 UINT16 ClassID;\r
79 UINT8 CacheLineSize;\r
80 UINT8 LatencyTimer;\r
81 UINT8 HeaderType; // must be zero to impose this structure...\r
82 UINT8 BIST; // built-in self test\r
83 UINT32 BaseAddressReg_0; // memory mapped address\r
84 UINT32 BaseAddressReg_1; //io mapped address, Base IO address\r
85 UINT32 BaseAddressReg_2; // option rom address\r
86 UINT32 BaseAddressReg_3;\r
87 UINT32 BaseAddressReg_4;\r
88 UINT32 BaseAddressReg_5;\r
89 UINT32 CardBusCISPtr;\r
90 UINT16 SubVendorID;\r
91 UINT16 SubSystemID;\r
92 UINT32 ExpansionROMBaseAddr;\r
93 UINT8 CapabilitiesPtr;\r
94 UINT8 reserved1;\r
95 UINT16 Reserved2;\r
96 UINT32 Reserved3;\r
97 UINT8 int_line;\r
98 UINT8 int_pin;\r
99 UINT8 Min_gnt;\r
100 UINT8 Max_lat;\r
101} PCI_CONFIG_HEADER;\r
102#pragma pack()\r
103\r
104//-------------------------------------------------------------------------\r
105// Offsets to the various registers.\r
106// All accesses need not be longword aligned.\r
107//-------------------------------------------------------------------------\r
108enum speedo_offsets {\r
109 SCBStatus = 0, SCBCmd = 2, // Rx/Command Unit command and status.\r
110 SCBPointer = 4, // General purpose pointer.\r
111 SCBPort = 8, // Misc. commands and operands.\r
112 SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.\r
113 SCBCtrlMDI = 16, // MDI interface control.\r
114 SCBEarlyRx = 20, // Early receive byte count.\r
115 SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,\r
116 // offsets for general control registers (GCRs)\r
117 SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31\r
118};\r
119\r
120#define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2\r
121\r
122//-------------------------------------------------------------------------\r
123// Action commands - Commands that can be put in a command list entry.\r
124//-------------------------------------------------------------------------\r
125enum commands {\r
126 CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,\r
127 CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7,\r
128 CmdSuspend = 0x4000, /* Suspend after completion. */\r
129 CmdIntr = 0x2000, /* Interrupt after completion. */\r
130 CmdTxFlex = 0x0008 /* Use "Flexible mode" for CmdTx command. */\r
131};\r
132\r
133//-------------------------------------------------------------------------\r
134// port commands\r
135//-------------------------------------------------------------------------\r
136#define PORT_RESET 0\r
137#define PORT_SELF_TEST 1\r
138#define POR_SELECTIVE_RESET 2\r
139#define PORT_DUMP_POINTER 2\r
140\r
141//-------------------------------------------------------------------------\r
142// SCB Command Word bit definitions\r
143//-------------------------------------------------------------------------\r
144//- CUC fields\r
145#define CU_START 0x0010\r
146#define CU_RESUME 0x0020\r
147#define CU_STATSADDR 0x0040\r
148#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */\r
149#define CU_CMD_BASE 0x0060 /* Base address to add to add CU commands. */\r
150#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */\r
151\r
152//- RUC fields\r
153#define RX_START 0x0001\r
154#define RX_RESUME 0x0002\r
155#define RX_ABORT 0x0004\r
156#define RX_ADDR_LOAD 0x0006 /* load ru_base_reg */\r
157#define RX_RESUMENR 0x0007\r
158\r
159// Interrupt fields (assuming byte addressing)\r
160#define INT_MASK 0x0100\r
161#define DRVR_INT 0x0200 /* Driver generated interrupt. */\r
162\r
163//- CB Status Word\r
164#define CMD_STATUS_COMPLETE 0x8000\r
165#define RX_STATUS_COMPLETE 0x8000\r
166#define CMD_STATUS_MASK 0xF000\r
167\r
168//-------------------------------------------------------------------------\r
169//- SCB Status bits:\r
170// Interrupts are ACKed by writing to the upper 6 interrupt bits\r
171//-------------------------------------------------------------------------\r
172#define SCB_STATUS_MASK 0xFC00 // bits 2-7 - STATUS/ACK Mask\r
173#define SCB_STATUS_CX_TNO 0x8000 // BIT_15 - CX or TNO Interrupt\r
174#define SCB_STATUS_FR 0x4000 // BIT_14 - FR Interrupt\r
175#define SCB_STATUS_CNA 0x2000 // BIT_13 - CNA Interrupt\r
176#define SCB_STATUS_RNR 0x1000 // BIT_12 - RNR Interrupt\r
177#define SCB_STATUS_MDI 0x0800 // BIT_11 - MDI R/W Done Interrupt\r
178#define SCB_STATUS_SWI 0x0400 // BIT_10 - SWI Interrupt\r
179\r
180// CU STATUS: bits 6 & 7\r
181#define SCB_STATUS_CU_MASK 0x00C0 // bits 6 & 7\r
182#define SCB_STATUS_CU_IDLE 0x0000 // 00\r
183#define SCB_STATUS_CU_SUSPEND 0x0040 // 01\r
184#define SCB_STATUS_CU_ACTIVE 0x0080 // 10\r
185\r
186// RU STATUS: bits 2-5\r
187#define SCB_RUS_IDLE 0x0000\r
188#define SCB_RUS_SUSPENDED 0x0004 // bit 2\r
189#define SCB_RUS_NO_RESOURCES 0x0008 // bit 3\r
190#define SCB_RUS_READY 0x0010 // bit 4\r
191\r
192//-------------------------------------------------------------------------\r
193// Bit Mask definitions\r
194//-------------------------------------------------------------------------\r
195#define BIT_0 0x0001\r
196#define BIT_1 0x0002\r
197#define BIT_2 0x0004\r
198#define BIT_3 0x0008\r
199#define BIT_4 0x0010\r
200#define BIT_5 0x0020\r
201#define BIT_6 0x0040\r
202#define BIT_7 0x0080\r
203#define BIT_8 0x0100\r
204#define BIT_9 0x0200\r
205#define BIT_10 0x0400\r
206#define BIT_11 0x0800\r
207#define BIT_12 0x1000\r
208#define BIT_13 0x2000\r
209#define BIT_14 0x4000\r
210#define BIT_15 0x8000\r
211#define BIT_24 0x01000000\r
212#define BIT_28 0x10000000\r
213\r
214\r
215//-------------------------------------------------------------------------\r
216// MDI Control register bit definitions\r
217//-------------------------------------------------------------------------\r
218#define MDI_DATA_MASK BIT_0_15 // MDI Data port\r
219#define MDI_REG_ADDR BIT_16_20 // which MDI register to read/write\r
220#define MDI_PHY_ADDR BIT_21_25 // which PHY to read/write\r
221#define MDI_PHY_OPCODE BIT_26_27 // which PHY to read/write\r
222#define MDI_PHY_READY BIT_28 // PHY is ready for another MDI cycle\r
223#define MDI_PHY_INT_ENABLE BIT_29 // Assert INT at MDI cycle completion\r
224\r
225#define BIT_0_2 0x0007\r
226#define BIT_0_3 0x000F\r
227#define BIT_0_4 0x001F\r
228#define BIT_0_5 0x003F\r
229#define BIT_0_6 0x007F\r
230#define BIT_0_7 0x00FF\r
231#define BIT_0_8 0x01FF\r
232#define BIT_0_13 0x3FFF\r
233#define BIT_0_15 0xFFFF\r
234#define BIT_1_2 0x0006\r
235#define BIT_1_3 0x000E\r
236#define BIT_2_5 0x003C\r
237#define BIT_3_4 0x0018\r
238#define BIT_4_5 0x0030\r
239#define BIT_4_6 0x0070\r
240#define BIT_4_7 0x00F0\r
241#define BIT_5_7 0x00E0\r
242#define BIT_5_9 0x03E0\r
243#define BIT_5_12 0x1FE0\r
244#define BIT_5_15 0xFFE0\r
245#define BIT_6_7 0x00c0\r
246#define BIT_7_11 0x0F80\r
247#define BIT_8_10 0x0700\r
248#define BIT_9_13 0x3E00\r
249#define BIT_12_15 0xF000\r
250\r
251#define BIT_16_20 0x001F0000\r
252#define BIT_21_25 0x03E00000\r
253#define BIT_26_27 0x0C000000\r
254\r
255//-------------------------------------------------------------------------\r
256// MDI Control register opcode definitions\r
257//-------------------------------------------------------------------------\r
258#define MDI_WRITE 1 // Phy Write\r
259#define MDI_READ 2 // Phy read\r
260\r
261//-------------------------------------------------------------------------\r
262// PHY 100 MDI Register/Bit Definitions\r
263//-------------------------------------------------------------------------\r
264// MDI register set\r
265#define MDI_CONTROL_REG 0x00 // MDI control register\r
266#define MDI_STATUS_REG 0x01 // MDI Status regiser\r
267#define PHY_ID_REG_1 0x02 // Phy indentification reg (word 1)\r
268#define PHY_ID_REG_2 0x03 // Phy indentification reg (word 2)\r
269#define AUTO_NEG_ADVERTISE_REG 0x04 // Auto-negotiation advertisement\r
270#define AUTO_NEG_LINK_PARTNER_REG 0x05 // Auto-negotiation link partner ability\r
271#define AUTO_NEG_EXPANSION_REG 0x06 // Auto-negotiation expansion\r
272#define AUTO_NEG_NEXT_PAGE_REG 0x07 // Auto-negotiation next page transmit\r
273#define EXTENDED_REG_0 0x10 // Extended reg 0 (Phy 100 modes)\r
274#define EXTENDED_REG_1 0x14 // Extended reg 1 (Phy 100 error indications)\r
275#define NSC_CONG_CONTROL_REG 0x17 // National (TX) congestion control\r
276#define NSC_SPEED_IND_REG 0x19 // National (TX) speed indication\r
277\r
278// MDI Control register bit definitions\r
279#define MDI_CR_COLL_TEST_ENABLE BIT_7 // Collision test enable\r
280#define MDI_CR_FULL_HALF BIT_8 // FDX =1, half duplex =0\r
281#define MDI_CR_RESTART_AUTO_NEG BIT_9 // Restart auto negotiation\r
282#define MDI_CR_ISOLATE BIT_10 // Isolate PHY from MII\r
283#define MDI_CR_POWER_DOWN BIT_11 // Power down\r
284#define MDI_CR_AUTO_SELECT BIT_12 // Auto speed select enable\r
285#define MDI_CR_10_100 BIT_13 // 0 = 10Mbs, 1 = 100Mbs\r
286#define MDI_CR_LOOPBACK BIT_14 // 0 = normal, 1 = loopback\r
287#define MDI_CR_RESET BIT_15 // 0 = normal, 1 = PHY reset\r
288\r
289// MDI Status register bit definitions\r
290#define MDI_SR_EXT_REG_CAPABLE BIT_0 // Extended register capabilities\r
291#define MDI_SR_JABBER_DETECT BIT_1 // Jabber detected\r
292#define MDI_SR_LINK_STATUS BIT_2 // Link Status -- 1 = link\r
293#define MDI_SR_AUTO_SELECT_CAPABLE BIT_3 // Auto speed select capable\r
294#define MDI_SR_REMOTE_FAULT_DETECT BIT_4 // Remote fault detect\r
295#define MDI_SR_AUTO_NEG_COMPLETE BIT_5 // Auto negotiation complete\r
296#define MDI_SR_10T_HALF_DPX BIT_11 // 10BaseT Half Duplex capable\r
297#define MDI_SR_10T_FULL_DPX BIT_12 // 10BaseT full duplex capable\r
298#define MDI_SR_TX_HALF_DPX BIT_13 // TX Half Duplex capable\r
299#define MDI_SR_TX_FULL_DPX BIT_14 // TX full duplex capable\r
300#define MDI_SR_T4_CAPABLE BIT_15 // T4 capable\r
301\r
302// Auto-Negotiation advertisement register bit definitions\r
303#define NWAY_AD_SELCTOR_FIELD BIT_0_4 // identifies supported protocol\r
304#define NWAY_AD_ABILITY BIT_5_12 // technologies that are supported\r
305#define NWAY_AD_10T_HALF_DPX BIT_5 // 10BaseT Half Duplex capable\r
306#define NWAY_AD_10T_FULL_DPX BIT_6 // 10BaseT full duplex capable\r
307#define NWAY_AD_TX_HALF_DPX BIT_7 // TX Half Duplex capable\r
308#define NWAY_AD_TX_FULL_DPX BIT_8 // TX full duplex capable\r
309#define NWAY_AD_T4_CAPABLE BIT_9 // T4 capable\r
310#define NWAY_AD_REMOTE_FAULT BIT_13 // indicates local remote fault\r
311#define NWAY_AD_RESERVED BIT_14 // reserved\r
312#define NWAY_AD_NEXT_PAGE BIT_15 // Next page (not supported)\r
313\r
314// Auto-Negotiation link partner ability register bit definitions\r
315#define NWAY_LP_SELCTOR_FIELD BIT_0_4 // identifies supported protocol\r
316#define NWAY_LP_ABILITY BIT_5_9 // technologies that are supported\r
317#define NWAY_LP_REMOTE_FAULT BIT_13 // indicates partner remote fault\r
318#define NWAY_LP_ACKNOWLEDGE BIT_14 // acknowledge\r
319#define NWAY_LP_NEXT_PAGE BIT_15 // Next page (not supported)\r
320\r
321// Auto-Negotiation expansion register bit definitions\r
322#define NWAY_EX_LP_NWAY BIT_0 // link partner is NWAY\r
323#define NWAY_EX_PAGE_RECEIVED BIT_1 // link code word received\r
324#define NWAY_EX_NEXT_PAGE_ABLE BIT_2 // local is next page able\r
325#define NWAY_EX_LP_NEXT_PAGE_ABLE BIT_3 // partner is next page able\r
326#define NWAY_EX_PARALLEL_DET_FLT BIT_4 // parallel detection fault\r
327#define NWAY_EX_RESERVED BIT_5_15 // reserved\r
328\r
329\r
330// PHY 100 Extended Register 0 bit definitions\r
331#define PHY_100_ER0_FDX_INDIC BIT_0 // 1 = FDX, 0 = half duplex\r
332#define PHY_100_ER0_SPEED_INDIC BIT_1 // 1 = 100mbs, 0= 10mbs\r
333#define PHY_100_ER0_WAKE_UP BIT_2 // Wake up DAC\r
334#define PHY_100_ER0_RESERVED BIT_3_4 // Reserved\r
335#define PHY_100_ER0_REV_CNTRL BIT_5_7 // Revsion control (A step = 000)\r
336#define PHY_100_ER0_FORCE_FAIL BIT_8 // Force Fail is enabled\r
337#define PHY_100_ER0_TEST BIT_9_13 // Revsion control (A step = 000)\r
338#define PHY_100_ER0_LINKDIS BIT_14 // Link integrity test is disabled\r
339#define PHY_100_ER0_JABDIS BIT_15 // Jabber function is disabled\r
340\r
341\r
342// PHY 100 Extended Register 1 bit definitions\r
343#define PHY_100_ER1_RESERVED BIT_0_8 // Reserved\r
344#define PHY_100_ER1_CH2_DET_ERR BIT_9 // Channel 2 EOF detection error\r
345#define PHY_100_ER1_MANCH_CODE_ERR BIT_10 // Manchester code error\r
346#define PHY_100_ER1_EOP_ERR BIT_11 // EOP error\r
347#define PHY_100_ER1_BAD_CODE_ERR BIT_12 // bad code error\r
348#define PHY_100_ER1_INV_CODE_ERR BIT_13 // invalid code error\r
349#define PHY_100_ER1_DC_BAL_ERR BIT_14 // DC balance error\r
350#define PHY_100_ER1_PAIR_SKEW_ERR BIT_15 // Pair skew error\r
351\r
352// National Semiconductor TX phy congestion control register bit definitions\r
353#define NSC_TX_CONG_TXREADY BIT_10 // Makes TxReady an input\r
354#define NSC_TX_CONG_ENABLE BIT_8 // Enables congestion control\r
355#define NSC_TX_CONG_F_CONNECT BIT_5 // Enables congestion control\r
356\r
357// National Semiconductor TX phy speed indication register bit definitions\r
358#define NSC_TX_SPD_INDC_SPEED BIT_6 // 0 = 100mb, 1=10mb\r
359\r
360//-------------------------------------------------------------------------\r
361// Phy related constants\r
362//-------------------------------------------------------------------------\r
363#define PHY_503 0\r
364#define PHY_100_A 0x000003E0\r
365#define PHY_100_C 0x035002A8\r
366#define PHY_TX_ID 0x015002A8\r
367#define PHY_NSC_TX 0x5c002000\r
368#define PHY_OTHER 0xFFFF\r
369\r
370#define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF\r
371#define PARALLEL_DETECT 0\r
372#define N_WAY 1\r
373\r
374#define RENEGOTIATE_TIME 35 // (3.5 Seconds)\r
375\r
376#define CONNECTOR_AUTO 0\r
377#define CONNECTOR_TPE 1\r
378#define CONNECTOR_MII 2\r
379\r
380//-------------------------------------------------------------------------\r
381\r
382/* The Speedo3 Rx and Tx frame/buffer descriptors. */\r
383#pragma pack(1)\r
384struct CB_Header { /* A generic descriptor. */\r
385 UINT16 status; /* Offset 0. */\r
386 UINT16 command; /* Offset 2. */\r
387 UINT32 link; /* struct descriptor * */\r
388};\r
389\r
390/* transmit command block structure */\r
391#pragma pack(1)\r
392typedef struct s_TxCB {\r
393 struct CB_Header cb_header;\r
394 UINT32 PhysTBDArrayAddres; /* address of an array that contains\r
395 physical TBD pointers */\r
396 UINT16 ByteCount; /* immediate data count = 0 always */\r
397 UINT8 Threshold;\r
398 UINT8 TBDCount;\r
399 UINT8 ImmediateData[TX_BUFFER_SIZE];\r
400 /* following fields are not seen by the 82557 */\r
401 struct TBD {\r
402 UINT32 phys_buf_addr;\r
403 UINT32 buf_len;\r
404 } TBDArray[MAX_XMIT_FRAGMENTS];\r
405 UINT32 PhysArrayAddr; /* in case the one in the header is lost */\r
406 UINT32 PhysTCBAddress; /* for this TCB */\r
407 struct s_TxCB *NextTCBVirtualLinkPtr;\r
408 struct s_TxCB *PrevTCBVirtualLinkPtr;\r
409 UINT64 free_data_ptr; // to be given to the upper layer when this xmit completes1\r
410}TxCB;\r
411\r
412/* The Speedo3 Rx and Tx buffer descriptors. */\r
413#pragma pack(1)\r
414typedef struct s_RxFD { /* Receive frame descriptor. */\r
415 struct CB_Header cb_header;\r
416 UINT32 rx_buf_addr; /* VOID * */\r
417 UINT16 ActualCount;\r
418 UINT16 RFDSize;\r
419 UINT8 RFDBuffer[RX_BUFFER_SIZE];\r
420 UINT8 forwarded;\r
421 UINT8 junk[3];\r
422}RxFD;\r
423\r
424/* Elements of the RxFD.status word. */\r
425#define RX_COMPLETE 0x8000\r
426#define RX_FRAME_OK 0x2000\r
427\r
428/* Elements of the dump_statistics block. This block must be lword aligned. */\r
429#pragma pack(1)\r
430struct speedo_stats {\r
431 UINT32 tx_good_frames;\r
432 UINT32 tx_coll16_errs;\r
433 UINT32 tx_late_colls;\r
434 UINT32 tx_underruns;\r
435 UINT32 tx_lost_carrier;\r
436 UINT32 tx_deferred;\r
437 UINT32 tx_one_colls;\r
438 UINT32 tx_multi_colls;\r
439 UINT32 tx_total_colls;\r
440 UINT32 rx_good_frames;\r
441 UINT32 rx_crc_errs;\r
442 UINT32 rx_align_errs;\r
443 UINT32 rx_resource_errs;\r
444 UINT32 rx_overrun_errs;\r
445 UINT32 rx_colls_errs;\r
446 UINT32 rx_runt_errs;\r
447 UINT32 done_marker;\r
448};\r
449#pragma pack()\r
450\r
451\r
452struct Krn_Mem{\r
453 RxFD rx_ring[RX_BUFFER_COUNT];\r
454 TxCB tx_ring[TX_BUFFER_COUNT];\r
455 struct speedo_stats statistics;\r
456};\r
457#define MEMORY_NEEDED sizeof(struct Krn_Mem)\r
458\r
459/* The parameters for a CmdConfigure operation.\r
460 There are so many options that it would be difficult to document each bit.\r
461 We mostly use the default or recommended settings.\r
462*/\r
463\r
464/*\r
465 *--------------------------------------------------------------------------\r
466 * Configuration CB Parameter Bit Definitions\r
467 *--------------------------------------------------------------------------\r
468 */\r
469// - Byte 0 (Default Value = 16h)\r
470#define CFIG_BYTE_COUNT 0x16 // 22 Configuration Bytes\r
471\r
472//- Byte 1 (Default Value = 88h)\r
473#define CFIG_TXRX_FIFO_LIMIT 0x88\r
474\r
475//- Byte 2 (Default Value = 0)\r
476#define CFIG_ADAPTIVE_IFS 0\r
477\r
478//- Byte 3 (Default Value = 0, ALWAYS. This byte is RESERVED)\r
479#define CFIG_RESERVED 0\r
480\r
481//- Byte 4 (Default Value = 0. Default implies that Rx DMA cannot be\r
482//- preempted).\r
483#define CFIG_RXDMA_BYTE_COUNT 0\r
484\r
485//- Byte 5 (Default Value = 80h. Default implies that Tx DMA cannot be\r
486//- preempted. However, setting these counters is enabled.)\r
487#define CFIG_DMBC_ENABLE 0x80\r
488\r
489//- Byte 6 (Default Value = 33h. Late SCB enabled, No TNO interrupts,\r
490//- CNA interrupts and do not save bad frames.)\r
491#define CFIG_LATE_SCB 1 // BIT 0\r
492#define CFIG_TNO_INTERRUPT 0x4 // BIT 2\r
493#define CFIG_CI_INTERRUPT 0x8 // BIT 3\r
494#define CFIG_SAVE_BAD_FRAMES 0x80 // BIT_7\r
495\r
496//- Byte 7 (Default Value = 7h. Discard short frames automatically and\r
497//- attempt upto 3 retries on transmit.)\r
498#define CFIG_DISCARD_SHORTRX 0x00001\r
499#define CFIG_URUN_RETRY BIT_1 OR BIT_2\r
500\r
501//- Byte 8 (Default Value = 1. Enable MII mode.)\r
502#define CFIG_503_MII BIT_0\r
503\r
504//- Byte 9 (Default Value = 0, ALWAYS)\r
505\r
506//- Byte 10 (Default Value = 2Eh)\r
507#define CFIG_NSAI BIT_3\r
508#define CFIG_PREAMBLE_LENGTH BIT_5 ;- Bit 5-4 = 1-0\r
509#define CFIG_NO_LOOPBACK 0\r
510#define CFIG_INTERNAL_LOOPBACK BIT_6\r
511#define CFIG_EXT_LOOPBACK BIT_7\r
512#define CFIG_EXT_PIN_LOOPBACK BIT_6 OR BIT_7\r
513\r
514//- Byte 11 (Default Value = 0)\r
515#define CFIG_LINEAR_PRIORITY 0\r
516\r
517//- Byte 12 (Default Value = 60h)\r
518#define CFIG_LPRIORITY_MODE 0\r
519#define CFIG_IFS 6 ;- 6 * 16 = 96\r
520\r
521//- Byte 13 (Default Value = 0, ALWAYS)\r
522\r
523//- Byte 14 (Default Value = 0F2h, ALWAYS)\r
524\r
525//- Byte 15 (Default Value = E8h)\r
526#define CFIG_PROMISCUOUS_MODE BIT_0\r
527#define CFIG_BROADCAST_DISABLE BIT_1\r
528#define CFIG_CRS_CDT BIT_7\r
529\r
530//- Byte 16 (Default Value = 0, ALWAYS)\r
531\r
532//- Byte 17 (Default Value = 40h, ALWAYS)\r
533\r
534//- Byte 18 (Default Value = F2h)\r
535#define CFIG_STRIPPING BIT_0\r
536#define CFIG_PADDING BIT_1\r
537#define CFIG_RX_CRC_TRANSFER BIT_2\r
538\r
539//- Byte 19 (Default Value = 80h)\r
540#define CFIG_FORCE_FDX BIT_6\r
541#define CFIG_FDX_PIN_ENABLE BIT_7\r
542\r
543//- Byte 20 (Default Value = 3Fh)\r
544#define CFIG_MULTI_IA BIT_6\r
545\r
546//- Byte 21 (Default Value = 05)\r
547#define CFIG_MC_ALL BIT_3\r
548\r
549/*-----------------------------------------------------------------------*/\r
550#define D102_REVID 0x0b\r
551\r
552#define HALF_DUPLEX 1\r
553#define FULL_DUPLEX 2\r
554\r
555typedef struct s_data_instance {\r
556\r
557 UINT16 State; // stopped, started or initialized\r
558 UINT16 Bus;\r
559 UINT8 Device;\r
560 UINT8 Function;\r
561 UINT16 VendorID;\r
562 UINT16 DeviceID;\r
563 UINT16 RevID;\r
564 UINT16 SubVendorID;\r
565 UINT16 SubSystemID;\r
566\r
567 UINT8 PermNodeAddress[PXE_MAC_LENGTH];\r
568 UINT8 CurrentNodeAddress[PXE_MAC_LENGTH];\r
569 UINT8 BroadcastNodeAddress[PXE_MAC_LENGTH];\r
570 UINT32 Config[MAX_PCI_CONFIG_LEN];\r
571 UINT32 NVData[MAX_EEPROM_LEN];\r
572\r
573 UINT32 ioaddr;\r
574 UINT32 flash_addr;\r
575\r
576 UINT16 LinkSpeed; // actual link speed setting\r
577 UINT16 LinkSpeedReq; // requested (forced) link speed\r
578 UINT8 DuplexReq; // requested duplex\r
579 UINT8 Duplex; // Duplex set\r
580 UINT8 CableDetect; // 1 to detect and 0 not to detect the cable\r
581 UINT8 LoopBack;\r
582\r
583 UINT16 TxBufCnt;\r
584 UINT16 TxBufSize;\r
585 UINT16 RxBufCnt;\r
586 UINT16 RxBufSize;\r
587 UINT32 RxTotals;\r
588 UINT32 TxTotals;\r
589\r
590 UINT16 int_mask;\r
591 UINT16 Int_Status;\r
592 UINT16 PhyRecord[2]; // primary and secondary PHY record registers from eeprom\r
593 UINT8 PhyAddress;\r
594 UINT8 int_num;\r
595 UINT16 NVData_Len;\r
596 UINT32 MemoryLength;\r
597\r
598 RxFD *rx_ring; // array of rx buffers\r
599 TxCB *tx_ring; // array of tx buffers\r
600 struct speedo_stats *statistics;\r
601 TxCB *FreeTxHeadPtr;\r
602 TxCB *FreeTxTailPtr;\r
603 RxFD *RFDTailPtr;\r
604\r
605 UINT64 rx_phy_addr; // physical addresses\r
606 UINT64 tx_phy_addr;\r
607 UINT64 stat_phy_addr;\r
608 UINT64 MemoryPtr;\r
609 UINT64 Mapped_MemoryPtr;\r
610\r
611 UINT64 xmit_done[TX_BUFFER_COUNT << 1]; // circular buffer\r
612 UINT16 xmit_done_head; // index into the xmit_done array\r
613 UINT16 xmit_done_tail; // where are we filling now (index into xmit_done)\r
614 UINT16 cur_rx_ind; // current RX Q head index\r
615 UINT16 FreeCBCount;\r
616\r
617 BOOLEAN in_interrupt;\r
618 BOOLEAN in_transmit;\r
619 BOOLEAN Receive_Started;\r
620 UINT8 Rx_Filter;\r
621 UINT8 VersionFlag; // UNDI30 or UNDI31??\r
622 UINT8 rsvd[3];\r
623\r
624 struct mc{\r
625 UINT16 reserved [3]; // padding for this structure to make it 8 byte aligned\r
626 UINT16 list_len;\r
627 UINT8 mc_list[MAX_MCAST_ADDRESS_CNT][PXE_MAC_LENGTH]; // 8*32 is the size\r
628 } mcast_list;\r
629\r
630 UINT64 Unique_ID;\r
631\r
632 EFI_PCI_IO_PROTOCOL *Io_Function;\r
633 //\r
634 // Original PCI attributes\r
635 //\r
636 UINT64 OriginalPciAttributes;\r
637\r
638 VOID (*Delay_30)(UINTN); // call back routine\r
639 VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r
640 VOID (*Block_30)(UINT32 enable); // call back routine\r
641 VOID (*Mem_Io_30)(UINT8 read_write, UINT8 len, UINT64 port, UINT64 buf_addr);\r
642 VOID (*Delay)(UINT64, UINTN); // call back routine\r
643 VOID (*Virt2Phys)(UINT64 unq_id, UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r
644 VOID (*Block)(UINT64 unq_id, UINT32 enable); // call back routine\r
645 VOID (*Mem_Io)(UINT64 unq_id, UINT8 read_write, UINT8 len, UINT64 port,\r
646 UINT64 buf_addr);\r
647 VOID (*Map_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
648 UINT32 Direction, UINT64 mapped_addr);\r
649 VOID (*UnMap_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
650 UINT32 Direction, UINT64 mapped_addr);\r
651 VOID (*Sync_Mem)(UINT64 unq_id, UINT64 virtual_addr,\r
652 UINT32 size, UINT32 Direction, UINT64 mapped_addr);\r
653} NIC_DATA_INSTANCE;\r
654\r
655#pragma pack(1)\r
656struct MC_CB_STRUCT{\r
657 UINT16 count;\r
658 UINT8 m_list[MAX_MCAST_ADDRESS_CNT][ETHER_MAC_ADDR_LEN];\r
659};\r
660#pragma pack()\r
661\r
662#define FOUR_GIGABYTE (UINT64)0x100000000ULL\r
663\r
664#endif\r
665\r
EFI Development Kit II mirror for PVE