OptionRomPkg/UndiRuntimeDxe/E100b.h

   1 /** @file
   2   Definitions for network adapter card.
   3
   4 Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef _E100B_H_
  10 #define _E100B_H_
  11
  12 // pci config offsets:
  13
  14 #define RX_BUFFER_COUNT 32
  15 #define TX_BUFFER_COUNT 32
  16
  17 #define PCI_VENDOR_ID_INTEL 0x8086
  18 #define PCI_DEVICE_ID_INTEL_82557 0x1229
  19 #define D100_VENDOR_ID   0x8086
  20 #define D100_DEVICE_ID   0x1229
  21 #define D102_DEVICE_ID   0x2449
  22
  23 #define ICH3_DEVICE_ID_1   0x1031
  24 #define ICH3_DEVICE_ID_2   0x1032
  25 #define ICH3_DEVICE_ID_3   0x1033
  26 #define ICH3_DEVICE_ID_4   0x1034
  27 #define ICH3_DEVICE_ID_5   0x1035
  28 #define ICH3_DEVICE_ID_6   0x1036
  29 #define ICH3_DEVICE_ID_7   0x1037
  30 #define ICH3_DEVICE_ID_8   0x1038
  31
  32 #define SPEEDO_DEVICE_ID   0x1227
  33 #define SPLASH1_DEVICE_ID   0x1226
  34
  35
  36 // bit fields for the command
  37 #define PCI_COMMAND_MASTER  0x04  // bit 2
  38 #define PCI_COMMAND_IO    0x01  // bit 0
  39 #define PCI_COMMAND  0x04
  40 #define PCI_LATENCY_TIMER  0x0D
  41
  42 #define ETHER_MAC_ADDR_LEN 6
  43 #ifdef AVL_XXX
  44 #define ETHER_HEADER_LEN 14
  45 // media interface type
  46 // #define INTERFACE_TYPE "
  47
  48 // Hardware type values
  49 #define HW_ETHER_TYPE    1
  50 #define HW_EXPERIMENTAL_ETHER_TYPE 2
  51 #define HW_IEEE_TYPE    6
  52 #define HW_ARCNET_TYPE     7
  53
  54 #endif  // AVL_XXX
  55
  56 #define MAX_ETHERNET_PKT_SIZE 1514  // including eth header
  57 #define RX_BUFFER_SIZE 1536  // including crc and padding
  58 #define TX_BUFFER_SIZE 64
  59 #define ETH_MTU 1500  // does not include ethernet header length
  60
  61 #define SPEEDO3_TOTAL_SIZE 0x20
  62
  63 #pragma pack(1)
  64
  65 typedef struct eth {
  66   UINT8 dest_addr[PXE_HWADDR_LEN_ETHER];
  67   UINT8 src_addr[PXE_HWADDR_LEN_ETHER];
  68   UINT16 type;
  69 } EtherHeader;
  70
  71 #pragma pack(1)
  72 typedef struct CONFIG_HEADER {
  73   UINT16 VendorID;
  74   UINT16 DeviceID;
  75   UINT16 Command;
  76   UINT16 Status;
  77   UINT16 RevID;
  78   UINT16 ClassID;
  79   UINT8  CacheLineSize;
  80   UINT8  LatencyTimer;
  81   UINT8  HeaderType;    // must be zero to impose this structure...
  82   UINT8  BIST;  // built-in self test
  83   UINT32 BaseAddressReg_0;  // memory mapped address
  84   UINT32 BaseAddressReg_1;  //io mapped address, Base IO address
  85   UINT32 BaseAddressReg_2;  // option rom address
  86   UINT32 BaseAddressReg_3;
  87   UINT32 BaseAddressReg_4;
  88   UINT32 BaseAddressReg_5;
  89   UINT32 CardBusCISPtr;
  90   UINT16 SubVendorID;
  91   UINT16 SubSystemID;
  92   UINT32 ExpansionROMBaseAddr;
  93   UINT8 CapabilitiesPtr;
  94   UINT8 reserved1;
  95   UINT16 Reserved2;
  96   UINT32 Reserved3;
  97   UINT8 int_line;
  98   UINT8 int_pin;
  99   UINT8 Min_gnt;
 100   UINT8 Max_lat;
 101 } PCI_CONFIG_HEADER;
 102 #pragma pack()
 103
 104 //-------------------------------------------------------------------------
 105 // Offsets to the various registers.
 106 //   All accesses need not be longword aligned.
 107 //-------------------------------------------------------------------------
 108 enum speedo_offsets {
 109   SCBStatus = 0, SCBCmd = 2,     // Rx/Command Unit command and status.
 110   SCBPointer = 4,                // General purpose pointer.
 111   SCBPort = 8,                   // Misc. commands and operands.
 112   SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.
 113   SCBCtrlMDI = 16,               // MDI interface control.
 114   SCBEarlyRx = 20,               // Early receive byte count.
 115   SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,
 116   // offsets for general control registers (GCRs)
 117   SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31
 118 };
 119
 120 #define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2
 121
 122 //-------------------------------------------------------------------------
 123 // Action commands - Commands that can be put in a command list entry.
 124 //-------------------------------------------------------------------------
 125 enum commands {
 126   CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,
 127   CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7,
 128   CmdSuspend = 0x4000,    /* Suspend after completion. */
 129   CmdIntr = 0x2000,      /* Interrupt after completion. */
 130   CmdTxFlex = 0x0008      /* Use "Flexible mode" for CmdTx command. */
 131 };
 132
 133 //-------------------------------------------------------------------------
 134 // port commands
 135 //-------------------------------------------------------------------------
 136 #define PORT_RESET 0
 137 #define PORT_SELF_TEST 1
 138 #define POR_SELECTIVE_RESET 2
 139 #define PORT_DUMP_POINTER 2
 140
 141 //-------------------------------------------------------------------------
 142 // SCB Command Word bit definitions
 143 //-------------------------------------------------------------------------
 144 //- CUC fields
 145 #define   CU_START    0x0010
 146 #define   CU_RESUME    0x0020
 147 #define   CU_STATSADDR  0x0040
 148 #define   CU_SHOWSTATS  0x0050  /* Dump statistics counters. */
 149 #define   CU_CMD_BASE  0x0060  /* Base address to add to add CU commands. */
 150 #define   CU_DUMPSTATS  0x0070  /* Dump then reset stats counters. */
 151
 152 //- RUC fields
 153 #define   RX_START  0x0001
 154 #define   RX_RESUME  0x0002
 155 #define   RX_ABORT  0x0004
 156 #define   RX_ADDR_LOAD  0x0006  /* load ru_base_reg */
 157 #define   RX_RESUMENR  0x0007
 158
 159 // Interrupt fields (assuming byte addressing)
 160 #define INT_MASK  0x0100
 161 #define DRVR_INT  0x0200    /* Driver generated interrupt. */
 162
 163 //- CB Status Word
 164 #define CMD_STATUS_COMPLETE 0x8000
 165 #define RX_STATUS_COMPLETE 0x8000
 166 #define CMD_STATUS_MASK 0xF000
 167
 168 //-------------------------------------------------------------------------
 169 //- SCB Status bits:
 170 // Interrupts are ACKed by writing to the upper 6 interrupt bits
 171 //-------------------------------------------------------------------------
 172 #define SCB_STATUS_MASK        0xFC00 // bits 2-7 - STATUS/ACK Mask
 173 #define SCB_STATUS_CX_TNO      0x8000 // BIT_15  - CX or TNO Interrupt
 174 #define SCB_STATUS_FR          0x4000 // BIT_14 - FR Interrupt
 175 #define SCB_STATUS_CNA         0x2000 // BIT_13 - CNA Interrupt
 176 #define SCB_STATUS_RNR         0x1000 // BIT_12  - RNR Interrupt
 177 #define SCB_STATUS_MDI         0x0800 // BIT_11  - MDI R/W Done Interrupt
 178 #define SCB_STATUS_SWI         0x0400 // BIT_10  - SWI Interrupt
 179
 180 // CU STATUS: bits 6 & 7
 181 #define SCB_STATUS_CU_MASK     0x00C0 // bits 6 & 7
 182 #define SCB_STATUS_CU_IDLE     0x0000 // 00
 183 #define SCB_STATUS_CU_SUSPEND  0x0040 // 01
 184 #define SCB_STATUS_CU_ACTIVE   0x0080 // 10
 185
 186 // RU STATUS: bits 2-5
 187 #define SCB_RUS_IDLE         0x0000
 188 #define SCB_RUS_SUSPENDED    0x0004  // bit 2
 189 #define SCB_RUS_NO_RESOURCES   0x0008 // bit 3
 190 #define SCB_RUS_READY       0x0010 // bit 4
 191
 192 //-------------------------------------------------------------------------
 193 // Bit Mask definitions
 194 //-------------------------------------------------------------------------
 195 #define BIT_0       0x0001
 196 #define BIT_1       0x0002
 197 #define BIT_2       0x0004
 198 #define BIT_3       0x0008
 199 #define BIT_4       0x0010
 200 #define BIT_5       0x0020
 201 #define BIT_6       0x0040
 202 #define BIT_7       0x0080
 203 #define BIT_8       0x0100
 204 #define BIT_9       0x0200
 205 #define BIT_10      0x0400
 206 #define BIT_11      0x0800
 207 #define BIT_12      0x1000
 208 #define BIT_13      0x2000
 209 #define BIT_14      0x4000
 210 #define BIT_15      0x8000
 211 #define BIT_24      0x01000000
 212 #define BIT_28      0x10000000
 213
 214
 215 //-------------------------------------------------------------------------
 216 // MDI Control register bit definitions
 217 //-------------------------------------------------------------------------
 218 #define MDI_DATA_MASK           BIT_0_15        // MDI Data port
 219 #define MDI_REG_ADDR            BIT_16_20       // which MDI register to read/write
 220 #define MDI_PHY_ADDR            BIT_21_25       // which PHY to read/write
 221 #define MDI_PHY_OPCODE          BIT_26_27       // which PHY to read/write
 222 #define MDI_PHY_READY           BIT_28          // PHY is ready for another MDI cycle
 223 #define MDI_PHY_INT_ENABLE      BIT_29          // Assert INT at MDI cycle completion
 224
 225 #define BIT_0_2     0x0007
 226 #define BIT_0_3     0x000F
 227 #define BIT_0_4     0x001F
 228 #define BIT_0_5     0x003F
 229 #define BIT_0_6     0x007F
 230 #define BIT_0_7     0x00FF
 231 #define BIT_0_8     0x01FF
 232 #define BIT_0_13    0x3FFF
 233 #define BIT_0_15    0xFFFF
 234 #define BIT_1_2     0x0006
 235 #define BIT_1_3     0x000E
 236 #define BIT_2_5     0x003C
 237 #define BIT_3_4     0x0018
 238 #define BIT_4_5     0x0030
 239 #define BIT_4_6     0x0070
 240 #define BIT_4_7     0x00F0
 241 #define BIT_5_7     0x00E0
 242 #define BIT_5_9     0x03E0
 243 #define BIT_5_12    0x1FE0
 244 #define BIT_5_15    0xFFE0
 245 #define BIT_6_7     0x00c0
 246 #define BIT_7_11    0x0F80
 247 #define BIT_8_10    0x0700
 248 #define BIT_9_13    0x3E00
 249 #define BIT_12_15   0xF000
 250
 251 #define BIT_16_20   0x001F0000
 252 #define BIT_21_25   0x03E00000
 253 #define BIT_26_27   0x0C000000
 254
 255 //-------------------------------------------------------------------------
 256 // MDI Control register opcode definitions
 257 //-------------------------------------------------------------------------
 258 #define MDI_WRITE               1               // Phy Write
 259 #define MDI_READ                2               // Phy read
 260
 261 //-------------------------------------------------------------------------
 262 // PHY 100 MDI Register/Bit Definitions
 263 //-------------------------------------------------------------------------
 264 // MDI register set
 265 #define MDI_CONTROL_REG             0x00        // MDI control register
 266 #define MDI_STATUS_REG              0x01        // MDI Status regiser
 267 #define PHY_ID_REG_1                0x02        // Phy indentification reg (word 1)
 268 #define PHY_ID_REG_2                0x03        // Phy indentification reg (word 2)
 269 #define AUTO_NEG_ADVERTISE_REG      0x04        // Auto-negotiation advertisement
 270 #define AUTO_NEG_LINK_PARTNER_REG   0x05        // Auto-negotiation link partner ability
 271 #define AUTO_NEG_EXPANSION_REG      0x06        // Auto-negotiation expansion
 272 #define AUTO_NEG_NEXT_PAGE_REG      0x07        // Auto-negotiation next page transmit
 273 #define EXTENDED_REG_0              0x10        // Extended reg 0 (Phy 100 modes)
 274 #define EXTENDED_REG_1              0x14        // Extended reg 1 (Phy 100 error indications)
 275 #define NSC_CONG_CONTROL_REG        0x17        // National (TX) congestion control
 276 #define NSC_SPEED_IND_REG           0x19        // National (TX) speed indication
 277
 278 // MDI Control register bit definitions
 279 #define MDI_CR_COLL_TEST_ENABLE     BIT_7       // Collision test enable
 280 #define MDI_CR_FULL_HALF            BIT_8       // FDX =1, half duplex =0
 281 #define MDI_CR_RESTART_AUTO_NEG     BIT_9       // Restart auto negotiation
 282 #define MDI_CR_ISOLATE              BIT_10      // Isolate PHY from MII
 283 #define MDI_CR_POWER_DOWN           BIT_11      // Power down
 284 #define MDI_CR_AUTO_SELECT          BIT_12      // Auto speed select enable
 285 #define MDI_CR_10_100               BIT_13      // 0 = 10Mbs, 1 = 100Mbs
 286 #define MDI_CR_LOOPBACK             BIT_14      // 0 = normal, 1 = loopback
 287 #define MDI_CR_RESET                BIT_15      // 0 = normal, 1 = PHY reset
 288
 289 // MDI Status register bit definitions
 290 #define MDI_SR_EXT_REG_CAPABLE      BIT_0       // Extended register capabilities
 291 #define MDI_SR_JABBER_DETECT        BIT_1       // Jabber detected
 292 #define MDI_SR_LINK_STATUS          BIT_2       // Link Status -- 1 = link
 293 #define MDI_SR_AUTO_SELECT_CAPABLE  BIT_3       // Auto speed select capable
 294 #define MDI_SR_REMOTE_FAULT_DETECT  BIT_4       // Remote fault detect
 295 #define MDI_SR_AUTO_NEG_COMPLETE    BIT_5       // Auto negotiation complete
 296 #define MDI_SR_10T_HALF_DPX         BIT_11      // 10BaseT Half Duplex capable
 297 #define MDI_SR_10T_FULL_DPX         BIT_12      // 10BaseT full duplex capable
 298 #define MDI_SR_TX_HALF_DPX          BIT_13      // TX Half Duplex capable
 299 #define MDI_SR_TX_FULL_DPX          BIT_14      // TX full duplex capable
 300 #define MDI_SR_T4_CAPABLE           BIT_15      // T4 capable
 301
 302 // Auto-Negotiation advertisement register bit definitions
 303 #define NWAY_AD_SELCTOR_FIELD       BIT_0_4     // identifies supported protocol
 304 #define NWAY_AD_ABILITY             BIT_5_12    // technologies that are supported
 305 #define NWAY_AD_10T_HALF_DPX        BIT_5       // 10BaseT Half Duplex capable
 306 #define NWAY_AD_10T_FULL_DPX        BIT_6       // 10BaseT full duplex capable
 307 #define NWAY_AD_TX_HALF_DPX         BIT_7       // TX Half Duplex capable
 308 #define NWAY_AD_TX_FULL_DPX         BIT_8       // TX full duplex capable
 309 #define NWAY_AD_T4_CAPABLE          BIT_9       // T4 capable
 310 #define NWAY_AD_REMOTE_FAULT        BIT_13      // indicates local remote fault
 311 #define NWAY_AD_RESERVED            BIT_14      // reserved
 312 #define NWAY_AD_NEXT_PAGE           BIT_15      // Next page (not supported)
 313
 314 // Auto-Negotiation link partner ability register bit definitions
 315 #define NWAY_LP_SELCTOR_FIELD       BIT_0_4     // identifies supported protocol
 316 #define NWAY_LP_ABILITY             BIT_5_9     // technologies that are supported
 317 #define NWAY_LP_REMOTE_FAULT        BIT_13      // indicates partner remote fault
 318 #define NWAY_LP_ACKNOWLEDGE         BIT_14      // acknowledge
 319 #define NWAY_LP_NEXT_PAGE           BIT_15      // Next page (not supported)
 320
 321 // Auto-Negotiation expansion register bit definitions
 322 #define NWAY_EX_LP_NWAY             BIT_0       // link partner is NWAY
 323 #define NWAY_EX_PAGE_RECEIVED       BIT_1       // link code word received
 324 #define NWAY_EX_NEXT_PAGE_ABLE      BIT_2       // local is next page able
 325 #define NWAY_EX_LP_NEXT_PAGE_ABLE   BIT_3       // partner is next page able
 326 #define NWAY_EX_PARALLEL_DET_FLT    BIT_4       // parallel detection fault
 327 #define NWAY_EX_RESERVED            BIT_5_15    // reserved
 328
 329
 330 // PHY 100 Extended Register 0 bit definitions
 331 #define PHY_100_ER0_FDX_INDIC       BIT_0       // 1 = FDX, 0 = half duplex
 332 #define PHY_100_ER0_SPEED_INDIC     BIT_1       // 1 = 100mbs, 0= 10mbs
 333 #define PHY_100_ER0_WAKE_UP         BIT_2       // Wake up DAC
 334 #define PHY_100_ER0_RESERVED        BIT_3_4     // Reserved
 335 #define PHY_100_ER0_REV_CNTRL       BIT_5_7     // Revsion control (A step = 000)
 336 #define PHY_100_ER0_FORCE_FAIL      BIT_8       // Force Fail is enabled
 337 #define PHY_100_ER0_TEST            BIT_9_13    // Revsion control (A step = 000)
 338 #define PHY_100_ER0_LINKDIS         BIT_14      // Link integrity test is disabled
 339 #define PHY_100_ER0_JABDIS          BIT_15      // Jabber function is disabled
 340
 341
 342 // PHY 100 Extended Register 1 bit definitions
 343 #define PHY_100_ER1_RESERVED        BIT_0_8     // Reserved
 344 #define PHY_100_ER1_CH2_DET_ERR     BIT_9       // Channel 2 EOF detection error
 345 #define PHY_100_ER1_MANCH_CODE_ERR  BIT_10      // Manchester code error
 346 #define PHY_100_ER1_EOP_ERR         BIT_11      // EOP error
 347 #define PHY_100_ER1_BAD_CODE_ERR    BIT_12      // bad code error
 348 #define PHY_100_ER1_INV_CODE_ERR    BIT_13      // invalid code error
 349 #define PHY_100_ER1_DC_BAL_ERR      BIT_14      // DC balance error
 350 #define PHY_100_ER1_PAIR_SKEW_ERR   BIT_15      // Pair skew error
 351
 352 // National Semiconductor TX phy congestion control register bit definitions
 353 #define NSC_TX_CONG_TXREADY         BIT_10      // Makes TxReady an input
 354 #define NSC_TX_CONG_ENABLE          BIT_8       // Enables congestion control
 355 #define NSC_TX_CONG_F_CONNECT       BIT_5       // Enables congestion control
 356
 357 // National Semiconductor TX phy speed indication register bit definitions
 358 #define NSC_TX_SPD_INDC_SPEED       BIT_6       // 0 = 100mb, 1=10mb
 359
 360 //-------------------------------------------------------------------------
 361 // Phy related constants
 362 //-------------------------------------------------------------------------
 363 #define PHY_503                 0
 364 #define PHY_100_A               0x000003E0
 365 #define PHY_100_C               0x035002A8
 366 #define PHY_TX_ID               0x015002A8
 367 #define PHY_NSC_TX              0x5c002000
 368 #define PHY_OTHER               0xFFFF
 369
 370 #define PHY_MODEL_REV_ID_MASK   0xFFF0FFFF
 371 #define PARALLEL_DETECT         0
 372 #define N_WAY                   1
 373
 374 #define RENEGOTIATE_TIME        35 // (3.5 Seconds)
 375
 376 #define CONNECTOR_AUTO          0
 377 #define CONNECTOR_TPE           1
 378 #define CONNECTOR_MII           2
 379
 380 //-------------------------------------------------------------------------
 381
 382 /* The Speedo3 Rx and Tx frame/buffer descriptors. */
 383 #pragma pack(1)
 384 struct CB_Header {      /* A generic descriptor. */
 385   UINT16 status;    /* Offset 0. */
 386   UINT16 command;    /* Offset 2. */
 387   UINT32 link;          /* struct descriptor *  */
 388 };
 389
 390 /* transmit command block structure */
 391 #pragma pack(1)
 392 typedef struct s_TxCB {
 393   struct CB_Header cb_header;
 394   UINT32 PhysTBDArrayAddres;  /* address of an array that contains
 395                 physical TBD pointers */
 396   UINT16 ByteCount;  /* immediate data count = 0 always */
 397   UINT8 Threshold;
 398   UINT8 TBDCount;
 399   UINT8 ImmediateData[TX_BUFFER_SIZE];
 400   /* following fields are not seen by the 82557 */
 401   struct TBD {
 402     UINT32 phys_buf_addr;
 403     UINT32 buf_len;
 404     } TBDArray[MAX_XMIT_FRAGMENTS];
 405   UINT32 PhysArrayAddr;  /* in case the one in the header is lost */
 406   UINT32 PhysTCBAddress;    /* for this TCB */
 407   struct s_TxCB *NextTCBVirtualLinkPtr;
 408   struct s_TxCB *PrevTCBVirtualLinkPtr;
 409   UINT64 free_data_ptr;  // to be given to the upper layer when this xmit completes1
 410 }TxCB;
 411
 412 /* The Speedo3 Rx and Tx buffer descriptors. */
 413 #pragma pack(1)
 414 typedef struct s_RxFD {          /* Receive frame descriptor. */
 415   struct CB_Header cb_header;
 416   UINT32 rx_buf_addr;      /* VOID * */
 417   UINT16 ActualCount;
 418   UINT16 RFDSize;
 419   UINT8 RFDBuffer[RX_BUFFER_SIZE];
 420   UINT8 forwarded;
 421   UINT8 junk[3];
 422 }RxFD;
 423
 424 /* Elements of the RxFD.status word. */
 425 #define RX_COMPLETE 0x8000
 426 #define RX_FRAME_OK 0x2000
 427
 428 /* Elements of the dump_statistics block. This block must be lword aligned. */
 429 #pragma pack(1)
 430 struct speedo_stats {
 431   UINT32 tx_good_frames;
 432   UINT32 tx_coll16_errs;
 433   UINT32 tx_late_colls;
 434   UINT32 tx_underruns;
 435   UINT32 tx_lost_carrier;
 436   UINT32 tx_deferred;
 437   UINT32 tx_one_colls;
 438   UINT32 tx_multi_colls;
 439   UINT32 tx_total_colls;
 440   UINT32 rx_good_frames;
 441   UINT32 rx_crc_errs;
 442   UINT32 rx_align_errs;
 443   UINT32 rx_resource_errs;
 444   UINT32 rx_overrun_errs;
 445   UINT32 rx_colls_errs;
 446   UINT32 rx_runt_errs;
 447   UINT32 done_marker;
 448 };
 449 #pragma pack()
 450
 451
 452 struct Krn_Mem{
 453   RxFD rx_ring[RX_BUFFER_COUNT];
 454   TxCB tx_ring[TX_BUFFER_COUNT];
 455   struct speedo_stats statistics;
 456 };
 457 #define MEMORY_NEEDED  sizeof(struct Krn_Mem)
 458
 459 /* The parameters for a CmdConfigure operation.
 460    There are so many options that it would be difficult to document each bit.
 461    We mostly use the default or recommended settings.
 462 */
 463
 464 /*
 465  *--------------------------------------------------------------------------
 466  * Configuration CB Parameter Bit Definitions
 467  *--------------------------------------------------------------------------
 468  */
 469 // - Byte 0  (Default Value = 16h)
 470 #define CFIG_BYTE_COUNT    0x16       // 22 Configuration Bytes
 471
 472 //- Byte 1  (Default Value = 88h)
 473 #define CFIG_TXRX_FIFO_LIMIT  0x88
 474
 475 //- Byte 2  (Default Value = 0)
 476 #define CFIG_ADAPTIVE_IFS    0
 477
 478 //- Byte 3  (Default Value = 0, ALWAYS. This byte is RESERVED)
 479 #define CFIG_RESERVED        0
 480
 481 //- Byte 4  (Default Value = 0. Default implies that Rx DMA cannot be
 482 //-          preempted).
 483 #define CFIG_RXDMA_BYTE_COUNT      0
 484
 485 //- Byte 5  (Default Value = 80h. Default implies that Tx DMA cannot be
 486 //-          preempted. However, setting these counters is enabled.)
 487 #define CFIG_DMBC_ENABLE            0x80
 488
 489 //- Byte 6  (Default Value = 33h. Late SCB enabled, No TNO interrupts,
 490 //-          CNA interrupts and do not save bad frames.)
 491 #define CFIG_LATE_SCB               1  // BIT 0
 492 #define CFIG_TNO_INTERRUPT          0x4  // BIT 2
 493 #define CFIG_CI_INTERRUPT           0x8  // BIT 3
 494 #define CFIG_SAVE_BAD_FRAMES        0x80  // BIT_7
 495
 496 //- Byte 7  (Default Value = 7h. Discard short frames automatically and
 497 //-          attempt upto 3 retries on transmit.)
 498 #define CFIG_DISCARD_SHORTRX         0x00001
 499 #define CFIG_URUN_RETRY              BIT_1 OR BIT_2
 500
 501 //- Byte 8  (Default Value = 1. Enable MII mode.)
 502 #define CFIG_503_MII              BIT_0
 503
 504 //- Byte 9  (Default Value = 0, ALWAYS)
 505
 506 //- Byte 10 (Default Value = 2Eh)
 507 #define CFIG_NSAI                   BIT_3
 508 #define CFIG_PREAMBLE_LENGTH         BIT_5      ;- Bit 5-4  = 1-0
 509 #define CFIG_NO_LOOPBACK             0
 510 #define CFIG_INTERNAL_LOOPBACK       BIT_6
 511 #define CFIG_EXT_LOOPBACK            BIT_7
 512 #define CFIG_EXT_PIN_LOOPBACK        BIT_6 OR BIT_7
 513
 514 //- Byte 11 (Default Value = 0)
 515 #define CFIG_LINEAR_PRIORITY         0
 516
 517 //- Byte 12 (Default Value = 60h)
 518 #define CFIG_LPRIORITY_MODE          0
 519 #define CFIG_IFS                     6          ;- 6 * 16 = 96
 520
 521 //- Byte 13 (Default Value = 0, ALWAYS)
 522
 523 //- Byte 14 (Default Value = 0F2h, ALWAYS)
 524
 525 //- Byte 15 (Default Value = E8h)
 526 #define CFIG_PROMISCUOUS_MODE        BIT_0
 527 #define CFIG_BROADCAST_DISABLE       BIT_1
 528 #define CFIG_CRS_CDT                 BIT_7
 529
 530 //- Byte 16 (Default Value = 0, ALWAYS)
 531
 532 //- Byte 17 (Default Value = 40h, ALWAYS)
 533
 534 //- Byte 18 (Default Value = F2h)
 535 #define CFIG_STRIPPING               BIT_0
 536 #define CFIG_PADDING                 BIT_1
 537 #define CFIG_RX_CRC_TRANSFER         BIT_2
 538
 539 //- Byte 19 (Default Value = 80h)
 540 #define CFIG_FORCE_FDX               BIT_6
 541 #define CFIG_FDX_PIN_ENABLE          BIT_7
 542
 543 //- Byte 20 (Default Value = 3Fh)
 544 #define CFIG_MULTI_IA                BIT_6
 545
 546 //- Byte 21 (Default Value = 05)
 547 #define CFIG_MC_ALL                  BIT_3
 548
 549 /*-----------------------------------------------------------------------*/
 550 #define D102_REVID 0x0b
 551
 552 #define HALF_DUPLEX 1
 553 #define FULL_DUPLEX 2
 554
 555 typedef struct s_data_instance {
 556
 557   UINT16 State;  // stopped, started or initialized
 558   UINT16 Bus;
 559   UINT8 Device;
 560   UINT8 Function;
 561   UINT16 VendorID;
 562   UINT16 DeviceID;
 563   UINT16 RevID;
 564   UINT16 SubVendorID;
 565   UINT16 SubSystemID;
 566
 567   UINT8 PermNodeAddress[PXE_MAC_LENGTH];
 568   UINT8 CurrentNodeAddress[PXE_MAC_LENGTH];
 569   UINT8 BroadcastNodeAddress[PXE_MAC_LENGTH];
 570   UINT32 Config[MAX_PCI_CONFIG_LEN];
 571   UINT32 NVData[MAX_EEPROM_LEN];
 572
 573   UINT32 ioaddr;
 574   UINT32 flash_addr;
 575
 576   UINT16 LinkSpeed;     // actual link speed setting
 577   UINT16 LinkSpeedReq;  // requested (forced) link speed
 578   UINT8  DuplexReq;     // requested duplex
 579   UINT8  Duplex;        // Duplex set
 580   UINT8  CableDetect;   // 1 to detect and 0 not to detect the cable
 581   UINT8  LoopBack;
 582
 583   UINT16 TxBufCnt;
 584   UINT16 TxBufSize;
 585   UINT16 RxBufCnt;
 586   UINT16 RxBufSize;
 587   UINT32 RxTotals;
 588   UINT32 TxTotals;
 589
 590   UINT16 int_mask;
 591   UINT16 Int_Status;
 592   UINT16 PhyRecord[2];  // primary and secondary PHY record registers from eeprom
 593   UINT8  PhyAddress;
 594   UINT8  int_num;
 595   UINT16 NVData_Len;
 596   UINT32 MemoryLength;
 597
 598   RxFD *rx_ring;  // array of rx buffers
 599   TxCB *tx_ring;  // array of tx buffers
 600   struct speedo_stats *statistics;
 601   TxCB *FreeTxHeadPtr;
 602   TxCB *FreeTxTailPtr;
 603   RxFD *RFDTailPtr;
 604
 605   UINT64 rx_phy_addr;  // physical addresses
 606   UINT64 tx_phy_addr;
 607   UINT64 stat_phy_addr;
 608   UINT64 MemoryPtr;
 609   UINT64 Mapped_MemoryPtr;
 610
 611   UINT64 xmit_done[TX_BUFFER_COUNT << 1]; // circular buffer
 612   UINT16 xmit_done_head;  // index into the xmit_done array
 613   UINT16 xmit_done_tail;  // where are we filling now (index into xmit_done)
 614   UINT16 cur_rx_ind;  // current RX Q head index
 615   UINT16 FreeCBCount;
 616
 617   BOOLEAN in_interrupt;
 618   BOOLEAN in_transmit;
 619   BOOLEAN Receive_Started;
 620   UINT8 Rx_Filter;
 621   UINT8 VersionFlag;  // UNDI30 or UNDI31??
 622   UINT8 rsvd[3];
 623
 624   struct mc{
 625     UINT16 reserved [3]; // padding for this structure to make it 8 byte aligned
 626     UINT16 list_len;
 627     UINT8 mc_list[MAX_MCAST_ADDRESS_CNT][PXE_MAC_LENGTH]; // 8*32 is the size
 628   } mcast_list;
 629
 630   UINT64 Unique_ID;
 631
 632   EFI_PCI_IO_PROTOCOL   *Io_Function;
 633   //
 634   // Original PCI attributes
 635   //
 636   UINT64                OriginalPciAttributes;
 637
 638   VOID (*Delay_30)(UINTN);  // call back routine
 639   VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr);  // call back routine
 640   VOID (*Block_30)(UINT32 enable);  // call back routine
 641   VOID (*Mem_Io_30)(UINT8 read_write, UINT8 len, UINT64 port, UINT64 buf_addr);
 642   VOID (*Delay)(UINT64, UINTN);  // call back routine
 643   VOID (*Virt2Phys)(UINT64 unq_id, UINT64 virtual_addr, UINT64 physical_ptr);  // call back routine
 644   VOID (*Block)(UINT64 unq_id, UINT32 enable);  // call back routine
 645   VOID (*Mem_Io)(UINT64 unq_id, UINT8 read_write, UINT8 len, UINT64 port,
 646           UINT64 buf_addr);
 647   VOID (*Map_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
 648                    UINT32 Direction, UINT64 mapped_addr);
 649   VOID (*UnMap_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
 650             UINT32 Direction, UINT64 mapped_addr);
 651   VOID (*Sync_Mem)(UINT64 unq_id, UINT64 virtual_addr,
 652             UINT32 size, UINT32 Direction, UINT64 mapped_addr);
 653 } NIC_DATA_INSTANCE;
 654
 655 #pragma pack(1)
 656 struct MC_CB_STRUCT{
 657   UINT16 count;
 658   UINT8 m_list[MAX_MCAST_ADDRESS_CNT][ETHER_MAC_ADDR_LEN];
 659 };
 660 #pragma pack()
 661
 662 #define FOUR_GIGABYTE (UINT64)0x100000000ULL
 663
 664 #endif
 665