]>
Commit | Line | Data |
---|---|---|
1 | /**@file\r | |
2 | Platform PEI driver\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r | |
6 | \r | |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // The package level header files this module uses\r | |
19 | //\r | |
20 | #include <PiPei.h>\r | |
21 | \r | |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
25 | #include <Library/DebugLib.h>\r | |
26 | #include <Library/HobLib.h>\r | |
27 | #include <Library/IoLib.h>\r | |
28 | #include <Library/MemoryAllocationLib.h>\r | |
29 | #include <Library/PcdLib.h>\r | |
30 | #include <Library/PciLib.h>\r | |
31 | #include <Library/PeimEntryPoint.h>\r | |
32 | #include <Library/PeiServicesLib.h>\r | |
33 | #include <Library/QemuFwCfgLib.h>\r | |
34 | #include <Library/ResourcePublicationLib.h>\r | |
35 | #include <Guid/MemoryTypeInformation.h>\r | |
36 | #include <Ppi/MasterBootMode.h>\r | |
37 | #include <IndustryStandard/Pci22.h>\r | |
38 | #include <OvmfPlatforms.h>\r | |
39 | \r | |
40 | #include "Platform.h"\r | |
41 | #include "Cmos.h"\r | |
42 | \r | |
43 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
44 | { EfiACPIMemoryNVS, 0x004 },\r | |
45 | { EfiACPIReclaimMemory, 0x008 },\r | |
46 | { EfiReservedMemoryType, 0x004 },\r | |
47 | { EfiRuntimeServicesData, 0x024 },\r | |
48 | { EfiRuntimeServicesCode, 0x030 },\r | |
49 | { EfiBootServicesCode, 0x180 },\r | |
50 | { EfiBootServicesData, 0xF00 },\r | |
51 | { EfiMaxMemoryType, 0x000 }\r | |
52 | };\r | |
53 | \r | |
54 | \r | |
55 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r | |
56 | {\r | |
57 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
58 | &gEfiPeiMasterBootModePpiGuid,\r | |
59 | NULL\r | |
60 | }\r | |
61 | };\r | |
62 | \r | |
63 | \r | |
64 | UINT16 mHostBridgeDevId;\r | |
65 | \r | |
66 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r | |
67 | \r | |
68 | BOOLEAN mS3Supported = FALSE;\r | |
69 | \r | |
70 | \r | |
71 | VOID\r | |
72 | AddIoMemoryBaseSizeHob (\r | |
73 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
74 | UINT64 MemorySize\r | |
75 | )\r | |
76 | {\r | |
77 | BuildResourceDescriptorHob (\r | |
78 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
79 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
80 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
81 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
82 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
83 | MemoryBase,\r | |
84 | MemorySize\r | |
85 | );\r | |
86 | }\r | |
87 | \r | |
88 | VOID\r | |
89 | AddReservedMemoryBaseSizeHob (\r | |
90 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
91 | UINT64 MemorySize\r | |
92 | )\r | |
93 | {\r | |
94 | BuildResourceDescriptorHob (\r | |
95 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
96 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
97 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
98 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
99 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
100 | MemoryBase,\r | |
101 | MemorySize\r | |
102 | );\r | |
103 | }\r | |
104 | \r | |
105 | VOID\r | |
106 | AddIoMemoryRangeHob (\r | |
107 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
108 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
109 | )\r | |
110 | {\r | |
111 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
112 | }\r | |
113 | \r | |
114 | \r | |
115 | VOID\r | |
116 | AddMemoryBaseSizeHob (\r | |
117 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
118 | UINT64 MemorySize\r | |
119 | )\r | |
120 | {\r | |
121 | BuildResourceDescriptorHob (\r | |
122 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
123 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
124 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
125 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
126 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
127 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
128 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
129 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
130 | MemoryBase,\r | |
131 | MemorySize\r | |
132 | );\r | |
133 | }\r | |
134 | \r | |
135 | \r | |
136 | VOID\r | |
137 | AddMemoryRangeHob (\r | |
138 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
139 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
140 | )\r | |
141 | {\r | |
142 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
143 | }\r | |
144 | \r | |
145 | \r | |
146 | VOID\r | |
147 | AddUntestedMemoryBaseSizeHob (\r | |
148 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
149 | UINT64 MemorySize\r | |
150 | )\r | |
151 | {\r | |
152 | BuildResourceDescriptorHob (\r | |
153 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
154 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
155 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
156 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
157 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
158 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
159 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r | |
160 | MemoryBase,\r | |
161 | MemorySize\r | |
162 | );\r | |
163 | }\r | |
164 | \r | |
165 | \r | |
166 | VOID\r | |
167 | AddUntestedMemoryRangeHob (\r | |
168 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
169 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
170 | )\r | |
171 | {\r | |
172 | AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
173 | }\r | |
174 | \r | |
175 | VOID\r | |
176 | MemMapInitialization (\r | |
177 | VOID\r | |
178 | )\r | |
179 | {\r | |
180 | //\r | |
181 | // Create Memory Type Information HOB\r | |
182 | //\r | |
183 | BuildGuidDataHob (\r | |
184 | &gEfiMemoryTypeInformationGuid,\r | |
185 | mDefaultMemoryTypeInformation,\r | |
186 | sizeof(mDefaultMemoryTypeInformation)\r | |
187 | );\r | |
188 | \r | |
189 | //\r | |
190 | // Add PCI IO Port space available for PCI resource allocations.\r | |
191 | //\r | |
192 | BuildResourceDescriptorHob (\r | |
193 | EFI_RESOURCE_IO,\r | |
194 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
195 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
196 | 0xC000,\r | |
197 | 0x4000\r | |
198 | );\r | |
199 | \r | |
200 | //\r | |
201 | // Video memory + Legacy BIOS region\r | |
202 | //\r | |
203 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
204 | \r | |
205 | if (!mXen) {\r | |
206 | UINT32 TopOfLowRam;\r | |
207 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r | |
208 | \r | |
209 | //\r | |
210 | // address purpose size\r | |
211 | // ------------ -------- -------------------------\r | |
212 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
213 | // 0xFC000000 gap 44 MB\r | |
214 | // 0xFEC00000 IO-APIC 4 KB\r | |
215 | // 0xFEC01000 gap 1020 KB\r | |
216 | // 0xFED00000 HPET 1 KB\r | |
217 | // 0xFED00400 gap 1023 KB\r | |
218 | // 0xFEE00000 LAPIC 1 MB\r | |
219 | //\r | |
220 | AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r | |
221 | BASE_2GB : TopOfLowRam, 0xFC000000);\r | |
222 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r | |
223 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
224 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r | |
225 | }\r | |
226 | }\r | |
227 | \r | |
228 | \r | |
229 | VOID\r | |
230 | MiscInitialization (\r | |
231 | VOID\r | |
232 | )\r | |
233 | {\r | |
234 | UINTN PmCmd;\r | |
235 | UINTN Pmba;\r | |
236 | UINTN AcpiCtlReg;\r | |
237 | UINT8 AcpiEnBit;\r | |
238 | \r | |
239 | //\r | |
240 | // Disable A20 Mask\r | |
241 | //\r | |
242 | IoOr8 (0x92, BIT1);\r | |
243 | \r | |
244 | //\r | |
245 | // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r | |
246 | //\r | |
247 | BuildCpuHob (36, 16);\r | |
248 | \r | |
249 | //\r | |
250 | // Determine platform type and save Host Bridge DID to PCD\r | |
251 | //\r | |
252 | switch (mHostBridgeDevId) {\r | |
253 | case INTEL_82441_DEVICE_ID:\r | |
254 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r | |
255 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r | |
256 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r | |
257 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
258 | break;\r | |
259 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
260 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r | |
261 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r | |
262 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r | |
263 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
264 | break;\r | |
265 | default:\r | |
266 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
267 | __FUNCTION__, mHostBridgeDevId));\r | |
268 | ASSERT (FALSE);\r | |
269 | return;\r | |
270 | }\r | |
271 | PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r | |
272 | \r | |
273 | //\r | |
274 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r | |
275 | // has been configured (e.g., by Xen) and skip the setup here.\r | |
276 | // This matches the logic in AcpiTimerLibConstructor ().\r | |
277 | //\r | |
278 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r | |
279 | //\r | |
280 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r | |
281 | // 1. set PMBA\r | |
282 | //\r | |
283 | PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r | |
284 | \r | |
285 | //\r | |
286 | // 2. set PCICMD/IOSE\r | |
287 | //\r | |
288 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r | |
289 | \r | |
290 | //\r | |
291 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r | |
292 | //\r | |
293 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r | |
294 | }\r | |
295 | }\r | |
296 | \r | |
297 | \r | |
298 | VOID\r | |
299 | BootModeInitialization (\r | |
300 | VOID\r | |
301 | )\r | |
302 | {\r | |
303 | EFI_STATUS Status;\r | |
304 | \r | |
305 | if (CmosRead8 (0xF) == 0xFE) {\r | |
306 | mBootMode = BOOT_ON_S3_RESUME;\r | |
307 | }\r | |
308 | \r | |
309 | Status = PeiServicesSetBootMode (mBootMode);\r | |
310 | ASSERT_EFI_ERROR (Status);\r | |
311 | \r | |
312 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
313 | ASSERT_EFI_ERROR (Status);\r | |
314 | }\r | |
315 | \r | |
316 | \r | |
317 | VOID\r | |
318 | ReserveEmuVariableNvStore (\r | |
319 | )\r | |
320 | {\r | |
321 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
322 | \r | |
323 | //\r | |
324 | // Allocate storage for NV variables early on so it will be\r | |
325 | // at a consistent address. Since VM memory is preserved\r | |
326 | // across reboots, this allows the NV variable storage to survive\r | |
327 | // a VM reboot.\r | |
328 | //\r | |
329 | VariableStore =\r | |
330 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
331 | AllocateAlignedRuntimePages (\r | |
332 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r | |
333 | PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r | |
334 | );\r | |
335 | DEBUG ((EFI_D_INFO,\r | |
336 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r | |
337 | VariableStore,\r | |
338 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r | |
339 | ));\r | |
340 | PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r | |
341 | }\r | |
342 | \r | |
343 | \r | |
344 | VOID\r | |
345 | DebugDumpCmos (\r | |
346 | VOID\r | |
347 | )\r | |
348 | {\r | |
349 | UINTN Loop;\r | |
350 | \r | |
351 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
352 | \r | |
353 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
354 | if ((Loop % 0x10) == 0) {\r | |
355 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
356 | }\r | |
357 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
358 | if ((Loop % 0x10) == 0xf) {\r | |
359 | DEBUG ((EFI_D_INFO, "\n"));\r | |
360 | }\r | |
361 | }\r | |
362 | }\r | |
363 | \r | |
364 | \r | |
365 | /**\r | |
366 | Perform Platform PEI initialization.\r | |
367 | \r | |
368 | @param FileHandle Handle of the file being invoked.\r | |
369 | @param PeiServices Describes the list of possible PEI Services.\r | |
370 | \r | |
371 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
372 | \r | |
373 | **/\r | |
374 | EFI_STATUS\r | |
375 | EFIAPI\r | |
376 | InitializePlatform (\r | |
377 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
378 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
379 | )\r | |
380 | {\r | |
381 | DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r | |
382 | \r | |
383 | DebugDumpCmos ();\r | |
384 | \r | |
385 | XenDetect ();\r | |
386 | \r | |
387 | if (QemuFwCfgS3Enabled ()) {\r | |
388 | DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r | |
389 | mS3Supported = TRUE;\r | |
390 | }\r | |
391 | \r | |
392 | BootModeInitialization ();\r | |
393 | \r | |
394 | PublishPeiMemory ();\r | |
395 | \r | |
396 | InitializeRamRegions ();\r | |
397 | \r | |
398 | if (mXen) {\r | |
399 | DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r | |
400 | InitializeXen ();\r | |
401 | }\r | |
402 | \r | |
403 | //\r | |
404 | // Query Host Bridge DID\r | |
405 | //\r | |
406 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
407 | \r | |
408 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
409 | ReserveEmuVariableNvStore ();\r | |
410 | \r | |
411 | PeiFvInitialization ();\r | |
412 | \r | |
413 | MemMapInitialization ();\r | |
414 | }\r | |
415 | \r | |
416 | MiscInitialization ();\r | |
417 | \r | |
418 | return EFI_SUCCESS;\r | |
419 | }\r |