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1 | /** @file\r | |
2 | This header file provides common definitions just for MCH using to avoid including extra module's file.\r | |
3 | \r | |
4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
5 | \r | |
6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | \r | |
8 | **/\r | |
9 | \r | |
10 | #ifndef _IOH_COMMON_DEFINITIONS_H_\r | |
11 | #define _IOH_COMMON_DEFINITIONS_H_\r | |
12 | \r | |
13 | //\r | |
14 | // PCI CONFIGURATION MAP REGISTER OFFSETS\r | |
15 | //\r | |
16 | #ifndef PCI_VID\r | |
17 | #define PCI_VID 0x0000 // Vendor ID Register\r | |
18 | #define PCI_DID 0x0002 // Device ID Register\r | |
19 | #define PCI_CMD 0x0004 // PCI Command Register\r | |
20 | #define PCI_STS 0x0006 // PCI Status Register\r | |
21 | #define PCI_RID 0x0008 // Revision ID Register\r | |
22 | #define PCI_IFT 0x0009 // Interface Type\r | |
23 | #define PCI_SCC 0x000A // Sub Class Code Register\r | |
24 | #define PCI_BCC 0x000B // Base Class Code Register\r | |
25 | #define PCI_CLS 0x000C // Cache Line Size\r | |
26 | #define PCI_PMLT 0x000D // Primary Master Latency Timer\r | |
27 | #define PCI_HDR 0x000E // Header Type Register\r | |
28 | #define PCI_BIST 0x000F // Built in Self Test Register\r | |
29 | #define PCI_BAR0 0x0010 // Base Address Register 0\r | |
30 | #define PCI_BAR1 0x0014 // Base Address Register 1\r | |
31 | #define PCI_BAR2 0x0018 // Base Address Register 2\r | |
32 | #define PCI_PBUS 0x0018 // Primary Bus Number Register\r | |
33 | #define PCI_SBUS 0x0019 // Secondary Bus Number Register\r | |
34 | #define PCI_SUBUS 0x001A // Subordinate Bus Number Register\r | |
35 | #define PCI_SMLT 0x001B // Secondary Master Latency Timer\r | |
36 | #define PCI_BAR3 0x001C // Base Address Register 3\r | |
37 | #define PCI_IOBASE 0x001C // I/O base Register\r | |
38 | #define PCI_IOLIMIT 0x001D // I/O Limit Register\r | |
39 | #define PCI_SECSTATUS 0x001E // Secondary Status Register\r | |
40 | #define PCI_BAR4 0x0020 // Base Address Register 4\r | |
41 | #define PCI_MEMBASE 0x0020 // Memory Base Register\r | |
42 | #define PCI_MEMLIMIT 0x0022 // Memory Limit Register\r | |
43 | #define PCI_BAR5 0x0024 // Base Address Register 5\r | |
44 | #define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register\r | |
45 | #define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register\r | |
46 | #define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32 bits\r | |
47 | #define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper 32 bits\r | |
48 | #define PCI_SVID 0x002C // Subsystem Vendor ID\r | |
49 | #define PCI_SID 0x002E // Subsystem ID\r | |
50 | #define PCI_IOBASE_U 0x0030 // I/O base Upper Register\r | |
51 | #define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register\r | |
52 | #define PCI_CAPP 0x0034 // Capabilities Pointer\r | |
53 | #define PCI_EROM 0x0038 // Expansion ROM Base Address\r | |
54 | #define PCI_INTLINE 0x003C // Interrupt Line Register\r | |
55 | #define PCI_INTPIN 0x003D // Interrupt Pin Register\r | |
56 | #define PCI_MAXGNT 0x003E // Max Grant Register\r | |
57 | #define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register\r | |
58 | #define PCI_MAXLAT 0x003F // Max Latency Register\r | |
59 | #endif\r | |
60 | //\r | |
61 | // Bit Difinitions\r | |
62 | //\r | |
63 | #ifndef BIT0\r | |
64 | #define BIT0 0x0001\r | |
65 | #define BIT1 0x0002\r | |
66 | #define BIT2 0x0004\r | |
67 | #define BIT3 0x0008\r | |
68 | #define BIT4 0x0010\r | |
69 | #define BIT5 0x0020\r | |
70 | #define BIT6 0x0040\r | |
71 | #define BIT7 0x0080\r | |
72 | #define BIT8 0x0100\r | |
73 | #define BIT9 0x0200\r | |
74 | #define BIT10 0x0400\r | |
75 | #define BIT11 0x0800\r | |
76 | #define BIT12 0x1000\r | |
77 | #define BIT13 0x2000\r | |
78 | #define BIT14 0x4000\r | |
79 | #define BIT15 0x8000\r | |
80 | #define BIT16 0x00010000\r | |
81 | #define BIT17 0x00020000\r | |
82 | #define BIT18 0x00040000\r | |
83 | #define BIT19 0x00080000\r | |
84 | #define BIT20 0x00100000\r | |
85 | #define BIT21 0x00200000\r | |
86 | #define BIT22 0x00400000\r | |
87 | #define BIT23 0x00800000\r | |
88 | #define BIT24 0x01000000\r | |
89 | #define BIT25 0x02000000\r | |
90 | #define BIT26 0x04000000\r | |
91 | #define BIT27 0x08000000\r | |
92 | #define BIT28 0x10000000\r | |
93 | #define BIT29 0x20000000\r | |
94 | #define BIT30 0x40000000\r | |
95 | #define BIT31 0x80000000\r | |
96 | #endif\r | |
97 | \r | |
98 | \r | |
99 | //\r | |
100 | // Common Memory mapped Io access macros ------------------------------------------\r | |
101 | //\r | |
102 | #define IohMmioAddress( BaseAddr, Register ) \\r | |
103 | ( (UINTN)BaseAddr + \\r | |
104 | (UINTN)(Register) \\r | |
105 | )\r | |
106 | \r | |
107 | //\r | |
108 | // UINT64\r | |
109 | //\r | |
110 | #define IohMmio64Ptr( BaseAddr, Register ) \\r | |
111 | ( (volatile UINT64 *)IohMmioAddress( BaseAddr, Register ) )\r | |
112 | \r | |
113 | #define IohMmio64( BaseAddr, Register ) \\r | |
114 | *IohMmio64Ptr( BaseAddr, Register )\r | |
115 | \r | |
116 | #define IohMmio64Or( BaseAddr, Register, OrData ) \\r | |
117 | IohMmio64( BaseAddr, Register ) = \\r | |
118 | (UINT64) ( \\r | |
119 | IohMmio64( BaseAddr, Register ) | \\r | |
120 | (UINT64)(OrData) \\r | |
121 | )\r | |
122 | \r | |
123 | #define IohMmio64And( BaseAddr, Register, AndData ) \\r | |
124 | IohMmio64( BaseAddr, Register ) = \\r | |
125 | (UINT64) ( \\r | |
126 | IohMmio64( BaseAddr, Register ) & \\r | |
127 | (UINT64)(AndData) \\r | |
128 | )\r | |
129 | \r | |
130 | #define IohMmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
131 | IohMmio64( BaseAddr, Register ) = \\r | |
132 | (UINT64) ( \\r | |
133 | ( IohMmio64( BaseAddr, Register ) & \\r | |
134 | (UINT64)(AndData) \\r | |
135 | ) | \\r | |
136 | (UINT64)(OrData) \\r | |
137 | )\r | |
138 | \r | |
139 | //\r | |
140 | // UINT32\r | |
141 | //\r | |
142 | #define IohMmio32Ptr( BaseAddr, Register ) \\r | |
143 | ( (volatile UINT32 *)IohMmioAddress( BaseAddr, Register ) )\r | |
144 | \r | |
145 | #define IohMmio32( BaseAddr, Register ) \\r | |
146 | *IohMmio32Ptr( BaseAddr, Register )\r | |
147 | \r | |
148 | #define IohMmio32Or( BaseAddr, Register, OrData ) \\r | |
149 | IohMmio32( BaseAddr, Register ) = \\r | |
150 | (UINT32) ( \\r | |
151 | IohMmio32( BaseAddr, Register ) | \\r | |
152 | (UINT32)(OrData) \\r | |
153 | )\r | |
154 | \r | |
155 | #define IohMmio32And( BaseAddr, Register, AndData ) \\r | |
156 | IohMmio32( BaseAddr, Register ) = \\r | |
157 | (UINT32) ( \\r | |
158 | IohMmio32( BaseAddr, Register ) & \\r | |
159 | (UINT32)(AndData) \\r | |
160 | )\r | |
161 | \r | |
162 | #define IohMmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
163 | IohMmio32( BaseAddr, Register ) = \\r | |
164 | (UINT32) ( \\r | |
165 | ( IohMmio32( BaseAddr, Register ) & \\r | |
166 | (UINT32)(AndData) \\r | |
167 | ) | \\r | |
168 | (UINT32)(OrData) \\r | |
169 | )\r | |
170 | //\r | |
171 | // UINT16\r | |
172 | //\r | |
173 | \r | |
174 | #define IohMmio16Ptr( BaseAddr, Register ) \\r | |
175 | ( (volatile UINT16 *)IohMmioAddress( BaseAddr, Register ) )\r | |
176 | \r | |
177 | #define IohMmio16( BaseAddr, Register ) \\r | |
178 | *IohMmio16Ptr( BaseAddr, Register )\r | |
179 | \r | |
180 | #define IohMmio16Or( BaseAddr, Register, OrData ) \\r | |
181 | IohMmio16( BaseAddr, Register ) = \\r | |
182 | (UINT16) ( \\r | |
183 | IohMmio16( BaseAddr, Register ) | \\r | |
184 | (UINT16)(OrData) \\r | |
185 | )\r | |
186 | \r | |
187 | #define IohMmio16And( BaseAddr, Register, AndData ) \\r | |
188 | IohMmio16( BaseAddr, Register ) = \\r | |
189 | (UINT16) ( \\r | |
190 | IohMmio16( BaseAddr, Register ) & \\r | |
191 | (UINT16)(AndData) \\r | |
192 | )\r | |
193 | \r | |
194 | #define IohMmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
195 | IohMmio16( BaseAddr, Register ) = \\r | |
196 | (UINT16) ( \\r | |
197 | ( IohMmio16( BaseAddr, Register ) & \\r | |
198 | (UINT16)(AndData) \\r | |
199 | ) | \\r | |
200 | (UINT16)(OrData) \\r | |
201 | )\r | |
202 | //\r | |
203 | // UINT8\r | |
204 | //\r | |
205 | #define IohMmio8Ptr( BaseAddr, Register ) \\r | |
206 | ( (volatile UINT8 *)IohMmioAddress( BaseAddr, Register ) )\r | |
207 | \r | |
208 | #define IohMmio8( BaseAddr, Register ) \\r | |
209 | *IohMmio8Ptr( BaseAddr, Register )\r | |
210 | \r | |
211 | #define IohMmio8Or( BaseAddr, Register, OrData ) \\r | |
212 | IohMmio8( BaseAddr, Register ) = \\r | |
213 | (UINT8) ( \\r | |
214 | IohMmio8( BaseAddr, Register ) | \\r | |
215 | (UINT8)(OrData) \\r | |
216 | )\r | |
217 | \r | |
218 | #define IohMmio8And( BaseAddr, Register, AndData ) \\r | |
219 | IohMmio8( BaseAddr, Register ) = \\r | |
220 | (UINT8) ( \\r | |
221 | IohMmio8( BaseAddr, Register ) & \\r | |
222 | (UINT8)(AndData) \\r | |
223 | )\r | |
224 | \r | |
225 | #define IohMmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
226 | IohMmio8( BaseAddr, Register ) = \\r | |
227 | (UINT8) ( \\r | |
228 | ( IohMmio8( BaseAddr, Register ) & \\r | |
229 | (UINT8)(AndData) \\r | |
230 | ) | \\r | |
231 | (UINT8)(OrData) \\r | |
232 | )\r | |
233 | \r | |
234 | //\r | |
235 | // Common Memory mapped Pci access macros ------------------------------------------\r | |
236 | //\r | |
237 | #define Ioh_PCI_EXPRESS_BASE_ADDRESS 0xE0000000\r | |
238 | \r | |
239 | \r | |
240 | #define IohMmPciAddress( Segment, Bus, Device, Function, Register ) \\r | |
241 | ( (UINTN)Ioh_PCI_EXPRESS_BASE_ADDRESS + \\r | |
242 | (UINTN)(Bus << 20) + \\r | |
243 | (UINTN)(Device << 15) + \\r | |
244 | (UINTN)(Function << 12) + \\r | |
245 | (UINTN)(Register) \\r | |
246 | )\r | |
247 | \r | |
248 | //\r | |
249 | // UINT32\r | |
250 | //\r | |
251 | #define IohMmPci32Ptr( Segment, Bus, Device, Function, Register ) \\r | |
252 | ( (volatile UINT32 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )\r | |
253 | \r | |
254 | #define IohMmPci32( Segment, Bus, Device, Function, Register ) \\r | |
255 | *IohMmPci32Ptr( Segment, Bus, Device, Function, Register )\r | |
256 | \r | |
257 | #define IohMmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \\r | |
258 | IohMmPci32( Segment, Bus, Device, Function, Register ) = \\r | |
259 | (UINT32) ( \\r | |
260 | IohMmPci32( Segment, Bus, Device, Function, Register ) | \\r | |
261 | (UINT32)(OrData) \\r | |
262 | )\r | |
263 | \r | |
264 | #define IohMmPci32And( Segment, Bus, Device, Function, Register, AndData ) \\r | |
265 | IohMmPci32( Segment, Bus, Device, Function, Register ) = \\r | |
266 | (UINT32) ( \\r | |
267 | IohMmPci32( Segment, Bus, Device, Function, Register ) & \\r | |
268 | (UINT32)(AndData) \\r | |
269 | )\r | |
270 | \r | |
271 | #define IohMmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r | |
272 | IohMmPci32( Segment, Bus, Device, Function, Register ) = \\r | |
273 | (UINT32) ( \\r | |
274 | ( IohMmPci32( Segment, Bus, Device, Function, Register ) & \\r | |
275 | (UINT32)(AndData) \\r | |
276 | ) | \\r | |
277 | (UINT32)(OrData) \\r | |
278 | )\r | |
279 | //\r | |
280 | // UINT16\r | |
281 | //\r | |
282 | #define IohMmPci16Ptr( Segment, Bus, Device, Function, Register ) \\r | |
283 | ( (volatile UINT16 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )\r | |
284 | \r | |
285 | #define IohMmPci16( Segment, Bus, Device, Function, Register ) \\r | |
286 | *IohMmPci16Ptr( Segment, Bus, Device, Function, Register )\r | |
287 | \r | |
288 | #define IohMmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \\r | |
289 | IohMmPci16( Segment, Bus, Device, Function, Register ) = \\r | |
290 | (UINT16) ( \\r | |
291 | IohMmPci16( Segment, Bus, Device, Function, Register ) | \\r | |
292 | (UINT16)(OrData) \\r | |
293 | )\r | |
294 | \r | |
295 | #define IohMmPci16And( Segment, Bus, Device, Function, Register, AndData ) \\r | |
296 | IohMmPci16( Segment, Bus, Device, Function, Register ) = \\r | |
297 | (UINT16) ( \\r | |
298 | IohMmPci16( Segment, Bus, Device, Function, Register ) & \\r | |
299 | (UINT16)(AndData) \\r | |
300 | )\r | |
301 | \r | |
302 | #define IohMmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r | |
303 | IohMmPci16( Segment, Bus, Device, Function, Register ) = \\r | |
304 | (UINT16) ( \\r | |
305 | ( IohMmPci16( Segment, Bus, Device, Function, Register ) & \\r | |
306 | (UINT16)(AndData) \\r | |
307 | ) | \\r | |
308 | (UINT16)(OrData) \\r | |
309 | )\r | |
310 | //\r | |
311 | // UINT8\r | |
312 | //\r | |
313 | #define IohMmPci8Ptr( Segment, Bus, Device, Function, Register ) \\r | |
314 | ( (volatile UINT8 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )\r | |
315 | \r | |
316 | #define IohMmPci8( Segment, Bus, Device, Function, Register ) \\r | |
317 | *IohMmPci8Ptr( Segment, Bus, Device, Function, Register )\r | |
318 | \r | |
319 | #define IohMmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \\r | |
320 | IohMmPci8( Segment, Bus, Device, Function, Register ) = \\r | |
321 | (UINT8) ( \\r | |
322 | IohMmPci8( Segment, Bus, Device, Function, Register ) | \\r | |
323 | (UINT8)(OrData) \\r | |
324 | )\r | |
325 | \r | |
326 | #define IohMmPci8And( Segment, Bus, Device, Function, Register, AndData ) \\r | |
327 | IohMmPci8( Segment, Bus, Device, Function, Register ) = \\r | |
328 | (UINT8) ( \\r | |
329 | IohMmPci8( Segment, Bus, Device, Function, Register ) & \\r | |
330 | (UINT8)(AndData) \\r | |
331 | )\r | |
332 | \r | |
333 | #define IohMmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r | |
334 | IohMmPci8( Segment, Bus, Device, Function, Register ) = \\r | |
335 | (UINT8) ( \\r | |
336 | ( IohMmPci8( Segment, Bus, Device, Function, Register ) & \\r | |
337 | (UINT8)(AndData) \\r | |
338 | ) | \\r | |
339 | (UINT8)(OrData) \\r | |
340 | )\r | |
341 | \r | |
342 | #endif\r |