QuarkSocPkg/QuarkSouthCluster/Include/IohCommonDefinitions.h

   1 /** @file
   2 This header file provides common definitions just for MCH using to avoid including extra module's file.
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef _IOH_COMMON_DEFINITIONS_H_
  11 #define _IOH_COMMON_DEFINITIONS_H_
  12
  13 //
  14 // PCI CONFIGURATION MAP REGISTER OFFSETS
  15 //
  16 #ifndef PCI_VID
  17 #define PCI_VID             0x0000        // Vendor ID Register
  18 #define PCI_DID             0x0002        // Device ID Register
  19 #define PCI_CMD             0x0004        // PCI Command Register
  20 #define PCI_STS             0x0006        // PCI Status Register
  21 #define PCI_RID             0x0008        // Revision ID Register
  22 #define PCI_IFT             0x0009        // Interface Type
  23 #define PCI_SCC             0x000A        // Sub Class Code Register
  24 #define PCI_BCC             0x000B        // Base Class Code Register
  25 #define PCI_CLS             0x000C        // Cache Line Size
  26 #define PCI_PMLT            0x000D        // Primary Master Latency Timer
  27 #define PCI_HDR             0x000E        // Header Type Register
  28 #define PCI_BIST            0x000F        // Built in Self Test Register
  29 #define PCI_BAR0            0x0010        // Base Address Register 0
  30 #define PCI_BAR1            0x0014        // Base Address Register 1
  31 #define PCI_BAR2            0x0018        // Base Address Register 2
  32 #define PCI_PBUS            0x0018        // Primary Bus Number Register
  33 #define PCI_SBUS            0x0019        // Secondary Bus Number Register
  34 #define PCI_SUBUS           0x001A        // Subordinate Bus Number Register
  35 #define PCI_SMLT            0x001B        // Secondary Master Latency Timer
  36 #define PCI_BAR3            0x001C        // Base Address Register 3
  37 #define PCI_IOBASE          0x001C        // I/O base Register
  38 #define PCI_IOLIMIT         0x001D        // I/O Limit Register
  39 #define PCI_SECSTATUS       0x001E        // Secondary Status Register
  40 #define PCI_BAR4            0x0020        // Base Address Register 4
  41 #define PCI_MEMBASE         0x0020        // Memory Base Register
  42 #define PCI_MEMLIMIT        0x0022        // Memory Limit Register
  43 #define PCI_BAR5            0x0024        // Base Address Register 5
  44 #define PCI_PRE_MEMBASE     0x0024        // Prefetchable memory Base register
  45 #define PCI_PRE_MEMLIMIT    0x0026        // Prefetchable memory Limit register
  46 #define PCI_PRE_MEMBASE_U   0x0028        // Prefetchable memory base upper 32 bits
  47 #define PCI_PRE_MEMLIMIT_U  0x002C        // Prefetchable memory limit upper 32 bits
  48 #define PCI_SVID            0x002C        // Subsystem Vendor ID
  49 #define PCI_SID             0x002E        // Subsystem ID
  50 #define PCI_IOBASE_U        0x0030        // I/O base Upper Register
  51 #define PCI_IOLIMIT_U       0x0032        // I/O Limit Upper Register
  52 #define PCI_CAPP            0x0034        // Capabilities Pointer
  53 #define PCI_EROM            0x0038        // Expansion ROM Base Address
  54 #define PCI_INTLINE         0x003C        // Interrupt Line Register
  55 #define PCI_INTPIN          0x003D        // Interrupt Pin Register
  56 #define PCI_MAXGNT          0x003E        // Max Grant Register
  57 #define PCI_BRIDGE_CNTL     0x003E        // Bridge Control Register
  58 #define PCI_MAXLAT          0x003F        // Max Latency Register
  59 #endif
  60 //
  61 // Bit Difinitions
  62 //
  63 #ifndef BIT0
  64 #define BIT0                     0x0001
  65 #define BIT1                     0x0002
  66 #define BIT2                     0x0004
  67 #define BIT3                     0x0008
  68 #define BIT4                     0x0010
  69 #define BIT5                     0x0020
  70 #define BIT6                     0x0040
  71 #define BIT7                     0x0080
  72 #define BIT8                     0x0100
  73 #define BIT9                     0x0200
  74 #define BIT10                    0x0400
  75 #define BIT11                    0x0800
  76 #define BIT12                    0x1000
  77 #define BIT13                    0x2000
  78 #define BIT14                    0x4000
  79 #define BIT15                    0x8000
  80 #define BIT16                0x00010000
  81 #define BIT17                0x00020000
  82 #define BIT18                0x00040000
  83 #define BIT19                0x00080000
  84 #define BIT20                0x00100000
  85 #define BIT21                0x00200000
  86 #define BIT22                0x00400000
  87 #define BIT23                0x00800000
  88 #define BIT24                0x01000000
  89 #define BIT25                0x02000000
  90 #define BIT26                0x04000000
  91 #define BIT27                0x08000000
  92 #define BIT28                0x10000000
  93 #define BIT29                0x20000000
  94 #define BIT30                0x40000000
  95 #define BIT31                0x80000000
  96 #endif
  97
  98
  99 //
 100 //  Common Memory mapped Io access macros ------------------------------------------
 101 //
 102 #define IohMmioAddress( BaseAddr, Register ) \
 103     ( (UINTN)BaseAddr + \
 104       (UINTN)(Register) \
 105     )
 106
 107 //
 108 // UINT64
 109 //
 110 #define IohMmio64Ptr( BaseAddr, Register ) \
 111     ( (volatile UINT64 *)IohMmioAddress( BaseAddr, Register ) )
 112
 113 #define IohMmio64( BaseAddr, Register ) \
 114     *IohMmio64Ptr( BaseAddr, Register )
 115
 116 #define IohMmio64Or( BaseAddr, Register, OrData ) \
 117     IohMmio64( BaseAddr, Register ) = \
 118       (UINT64) ( \
 119         IohMmio64( BaseAddr, Register ) | \
 120         (UINT64)(OrData) \
 121       )
 122
 123 #define IohMmio64And( BaseAddr, Register, AndData ) \
 124     IohMmio64( BaseAddr, Register ) = \
 125       (UINT64) ( \
 126         IohMmio64( BaseAddr, Register ) & \
 127         (UINT64)(AndData) \
 128       )
 129
 130 #define IohMmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \
 131     IohMmio64( BaseAddr, Register ) = \
 132       (UINT64) ( \
 133         ( IohMmio64( BaseAddr, Register ) & \
 134             (UINT64)(AndData) \
 135         ) | \
 136         (UINT64)(OrData) \
 137       )
 138
 139 //
 140 // UINT32
 141 //
 142 #define IohMmio32Ptr( BaseAddr, Register ) \
 143     ( (volatile UINT32 *)IohMmioAddress( BaseAddr, Register ) )
 144
 145 #define IohMmio32( BaseAddr, Register ) \
 146     *IohMmio32Ptr( BaseAddr, Register )
 147
 148 #define IohMmio32Or( BaseAddr, Register, OrData ) \
 149     IohMmio32( BaseAddr, Register ) = \
 150       (UINT32) ( \
 151         IohMmio32( BaseAddr, Register ) | \
 152         (UINT32)(OrData) \
 153       )
 154
 155 #define IohMmio32And( BaseAddr, Register, AndData ) \
 156     IohMmio32( BaseAddr, Register ) = \
 157       (UINT32) ( \
 158         IohMmio32( BaseAddr, Register ) & \
 159         (UINT32)(AndData) \
 160       )
 161
 162 #define IohMmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \
 163     IohMmio32( BaseAddr, Register ) = \
 164       (UINT32) ( \
 165         ( IohMmio32( BaseAddr, Register ) & \
 166             (UINT32)(AndData) \
 167         ) | \
 168         (UINT32)(OrData) \
 169       )
 170 //
 171 // UINT16
 172 //
 173
 174 #define IohMmio16Ptr( BaseAddr, Register ) \
 175     ( (volatile UINT16 *)IohMmioAddress( BaseAddr, Register ) )
 176
 177 #define IohMmio16( BaseAddr, Register ) \
 178     *IohMmio16Ptr( BaseAddr, Register )
 179
 180 #define IohMmio16Or( BaseAddr, Register, OrData ) \
 181     IohMmio16( BaseAddr, Register ) = \
 182       (UINT16) ( \
 183         IohMmio16( BaseAddr, Register ) | \
 184         (UINT16)(OrData) \
 185       )
 186
 187 #define IohMmio16And( BaseAddr, Register, AndData ) \
 188     IohMmio16( BaseAddr, Register ) = \
 189       (UINT16) ( \
 190         IohMmio16( BaseAddr, Register ) & \
 191         (UINT16)(AndData) \
 192       )
 193
 194 #define IohMmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \
 195     IohMmio16( BaseAddr, Register ) = \
 196       (UINT16) ( \
 197         ( IohMmio16( BaseAddr, Register ) & \
 198             (UINT16)(AndData) \
 199         ) | \
 200         (UINT16)(OrData) \
 201       )
 202 //
 203 // UINT8
 204 //
 205 #define IohMmio8Ptr( BaseAddr, Register ) \
 206     ( (volatile UINT8 *)IohMmioAddress( BaseAddr, Register ) )
 207
 208 #define IohMmio8( BaseAddr, Register ) \
 209     *IohMmio8Ptr( BaseAddr, Register )
 210
 211 #define IohMmio8Or( BaseAddr, Register, OrData ) \
 212     IohMmio8( BaseAddr, Register ) = \
 213       (UINT8) ( \
 214         IohMmio8( BaseAddr, Register ) | \
 215         (UINT8)(OrData) \
 216       )
 217
 218 #define IohMmio8And( BaseAddr, Register, AndData ) \
 219     IohMmio8( BaseAddr, Register ) = \
 220       (UINT8) ( \
 221         IohMmio8( BaseAddr, Register ) & \
 222         (UINT8)(AndData) \
 223       )
 224
 225 #define IohMmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \
 226     IohMmio8( BaseAddr, Register ) = \
 227       (UINT8) ( \
 228         ( IohMmio8( BaseAddr, Register ) & \
 229             (UINT8)(AndData) \
 230           ) | \
 231         (UINT8)(OrData) \
 232       )
 233
 234 //
 235 //  Common Memory mapped Pci access macros ------------------------------------------
 236 //
 237 #define Ioh_PCI_EXPRESS_BASE_ADDRESS  0xE0000000
 238
 239
 240 #define IohMmPciAddress( Segment, Bus, Device, Function, Register ) \
 241   ( (UINTN)Ioh_PCI_EXPRESS_BASE_ADDRESS + \
 242     (UINTN)(Bus << 20) + \
 243     (UINTN)(Device << 15) + \
 244     (UINTN)(Function << 12) + \
 245     (UINTN)(Register) \
 246   )
 247
 248 //
 249 // UINT32
 250 //
 251 #define IohMmPci32Ptr( Segment, Bus, Device, Function, Register ) \
 252   ( (volatile UINT32 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )
 253
 254 #define IohMmPci32( Segment, Bus, Device, Function, Register ) \
 255   *IohMmPci32Ptr( Segment, Bus, Device, Function, Register )
 256
 257 #define IohMmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
 258   IohMmPci32( Segment, Bus, Device, Function, Register ) = \
 259     (UINT32) ( \
 260       IohMmPci32( Segment, Bus, Device, Function, Register ) | \
 261       (UINT32)(OrData) \
 262     )
 263
 264 #define IohMmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
 265   IohMmPci32( Segment, Bus, Device, Function, Register ) = \
 266     (UINT32) ( \
 267       IohMmPci32( Segment, Bus, Device, Function, Register ) & \
 268       (UINT32)(AndData) \
 269     )
 270
 271 #define IohMmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
 272   IohMmPci32( Segment, Bus, Device, Function, Register ) = \
 273     (UINT32) ( \
 274       ( IohMmPci32( Segment, Bus, Device, Function, Register ) & \
 275           (UINT32)(AndData) \
 276       ) | \
 277       (UINT32)(OrData) \
 278     )
 279 //
 280 // UINT16
 281 //
 282 #define IohMmPci16Ptr( Segment, Bus, Device, Function, Register ) \
 283   ( (volatile UINT16 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )
 284
 285 #define IohMmPci16( Segment, Bus, Device, Function, Register ) \
 286   *IohMmPci16Ptr( Segment, Bus, Device, Function, Register )
 287
 288 #define IohMmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
 289   IohMmPci16( Segment, Bus, Device, Function, Register ) = \
 290     (UINT16) ( \
 291       IohMmPci16( Segment, Bus, Device, Function, Register ) | \
 292       (UINT16)(OrData) \
 293     )
 294
 295 #define IohMmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
 296   IohMmPci16( Segment, Bus, Device, Function, Register ) = \
 297     (UINT16) ( \
 298       IohMmPci16( Segment, Bus, Device, Function, Register ) & \
 299       (UINT16)(AndData) \
 300     )
 301
 302 #define IohMmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
 303   IohMmPci16( Segment, Bus, Device, Function, Register ) = \
 304     (UINT16) ( \
 305       ( IohMmPci16( Segment, Bus, Device, Function, Register ) & \
 306           (UINT16)(AndData) \
 307       ) | \
 308       (UINT16)(OrData) \
 309     )
 310 //
 311 // UINT8
 312 //
 313 #define IohMmPci8Ptr( Segment, Bus, Device, Function, Register ) \
 314   ( (volatile UINT8 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )
 315
 316 #define IohMmPci8( Segment, Bus, Device, Function, Register ) \
 317   *IohMmPci8Ptr( Segment, Bus, Device, Function, Register )
 318
 319 #define IohMmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
 320   IohMmPci8( Segment, Bus, Device, Function, Register ) = \
 321     (UINT8) ( \
 322       IohMmPci8( Segment, Bus, Device, Function, Register ) | \
 323       (UINT8)(OrData) \
 324     )
 325
 326 #define IohMmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
 327   IohMmPci8( Segment, Bus, Device, Function, Register ) = \
 328     (UINT8) ( \
 329       IohMmPci8( Segment, Bus, Device, Function, Register ) & \
 330       (UINT8)(AndData) \
 331     )
 332
 333 #define IohMmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
 334   IohMmPci8( Segment, Bus, Device, Function, Register ) = \
 335     (UINT8) ( \
 336       ( IohMmPci8( Segment, Bus, Device, Function, Register ) & \
 337           (UINT8)(AndData) \
 338         ) | \
 339       (UINT8)(OrData) \
 340     )
 341
 342 #endif