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1 | /** @file\r | |
2 | Public include file for Local APIC library.\r | |
3 | \r | |
4 | Local APIC library assumes local APIC is enabled. It does not\r | |
5 | handles cases where local APIC is disabled.\r | |
6 | \r | |
7 | Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r | |
8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
9 | \r | |
10 | **/\r | |
11 | \r | |
12 | #ifndef __LOCAL_APIC_LIB_H__\r | |
13 | #define __LOCAL_APIC_LIB_H__\r | |
14 | \r | |
15 | #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.\r | |
16 | #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.\r | |
17 | \r | |
18 | /**\r | |
19 | Retrieve the base address of local APIC.\r | |
20 | \r | |
21 | @return The base address of local APIC.\r | |
22 | \r | |
23 | **/\r | |
24 | UINTN\r | |
25 | EFIAPI\r | |
26 | GetLocalApicBaseAddress (\r | |
27 | VOID\r | |
28 | );\r | |
29 | \r | |
30 | /**\r | |
31 | Set the base address of local APIC.\r | |
32 | \r | |
33 | If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r | |
34 | \r | |
35 | @param[in] BaseAddress Local APIC base address to be set.\r | |
36 | \r | |
37 | **/\r | |
38 | VOID\r | |
39 | EFIAPI\r | |
40 | SetLocalApicBaseAddress (\r | |
41 | IN UINTN BaseAddress\r | |
42 | );\r | |
43 | \r | |
44 | /**\r | |
45 | Get the current local APIC mode.\r | |
46 | \r | |
47 | If local APIC is disabled, then ASSERT.\r | |
48 | \r | |
49 | @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r | |
50 | @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r | |
51 | **/\r | |
52 | UINTN\r | |
53 | EFIAPI\r | |
54 | GetApicMode (\r | |
55 | VOID\r | |
56 | );\r | |
57 | \r | |
58 | /**\r | |
59 | Set the current local APIC mode.\r | |
60 | \r | |
61 | If the specified local APIC mode is not valid, then ASSERT.\r | |
62 | If the specified local APIC mode can't be set as current, then ASSERT.\r | |
63 | \r | |
64 | @param ApicMode APIC mode to be set.\r | |
65 | \r | |
66 | @note This API must not be called from an interrupt handler or SMI handler.\r | |
67 | It may result in unpredictable behavior.\r | |
68 | **/\r | |
69 | VOID\r | |
70 | EFIAPI\r | |
71 | SetApicMode (\r | |
72 | IN UINTN ApicMode\r | |
73 | );\r | |
74 | \r | |
75 | /**\r | |
76 | Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r | |
77 | \r | |
78 | In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r | |
79 | In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r | |
80 | the 32-bit local APIC ID is returned as initial APIC ID.\r | |
81 | \r | |
82 | @return 32-bit initial local APIC ID of the executing processor.\r | |
83 | **/\r | |
84 | UINT32\r | |
85 | EFIAPI\r | |
86 | GetInitialApicId (\r | |
87 | VOID\r | |
88 | );\r | |
89 | \r | |
90 | /**\r | |
91 | Get the local APIC ID of the executing processor.\r | |
92 | \r | |
93 | @return 32-bit local APIC ID of the executing processor.\r | |
94 | **/\r | |
95 | UINT32\r | |
96 | EFIAPI\r | |
97 | GetApicId (\r | |
98 | VOID\r | |
99 | );\r | |
100 | \r | |
101 | /**\r | |
102 | Get the value of the local APIC version register.\r | |
103 | \r | |
104 | @return the value of the local APIC version register.\r | |
105 | **/\r | |
106 | UINT32\r | |
107 | EFIAPI\r | |
108 | GetApicVersion (\r | |
109 | VOID\r | |
110 | );\r | |
111 | \r | |
112 | /**\r | |
113 | Send a Fixed IPI to a specified target processor.\r | |
114 | \r | |
115 | This function returns after the IPI has been accepted by the target processor.\r | |
116 | \r | |
117 | @param ApicId The local APIC ID of the target processor.\r | |
118 | @param Vector The vector number of the interrupt being sent.\r | |
119 | **/\r | |
120 | VOID\r | |
121 | EFIAPI\r | |
122 | SendFixedIpi (\r | |
123 | IN UINT32 ApicId,\r | |
124 | IN UINT8 Vector\r | |
125 | );\r | |
126 | \r | |
127 | /**\r | |
128 | Send a Fixed IPI to all processors excluding self.\r | |
129 | \r | |
130 | This function returns after the IPI has been accepted by the target processors.\r | |
131 | \r | |
132 | @param Vector The vector number of the interrupt being sent.\r | |
133 | **/\r | |
134 | VOID\r | |
135 | EFIAPI\r | |
136 | SendFixedIpiAllExcludingSelf (\r | |
137 | IN UINT8 Vector\r | |
138 | );\r | |
139 | \r | |
140 | /**\r | |
141 | Send a SMI IPI to a specified target processor.\r | |
142 | \r | |
143 | This function returns after the IPI has been accepted by the target processor.\r | |
144 | \r | |
145 | @param ApicId Specify the local APIC ID of the target processor.\r | |
146 | **/\r | |
147 | VOID\r | |
148 | EFIAPI\r | |
149 | SendSmiIpi (\r | |
150 | IN UINT32 ApicId\r | |
151 | );\r | |
152 | \r | |
153 | /**\r | |
154 | Send a SMI IPI to all processors excluding self.\r | |
155 | \r | |
156 | This function returns after the IPI has been accepted by the target processors.\r | |
157 | **/\r | |
158 | VOID\r | |
159 | EFIAPI\r | |
160 | SendSmiIpiAllExcludingSelf (\r | |
161 | VOID\r | |
162 | );\r | |
163 | \r | |
164 | /**\r | |
165 | Send an INIT IPI to a specified target processor.\r | |
166 | \r | |
167 | This function returns after the IPI has been accepted by the target processor.\r | |
168 | \r | |
169 | @param ApicId Specify the local APIC ID of the target processor.\r | |
170 | **/\r | |
171 | VOID\r | |
172 | EFIAPI\r | |
173 | SendInitIpi (\r | |
174 | IN UINT32 ApicId\r | |
175 | );\r | |
176 | \r | |
177 | /**\r | |
178 | Send an INIT IPI to all processors excluding self.\r | |
179 | \r | |
180 | This function returns after the IPI has been accepted by the target processors.\r | |
181 | **/\r | |
182 | VOID\r | |
183 | EFIAPI\r | |
184 | SendInitIpiAllExcludingSelf (\r | |
185 | VOID\r | |
186 | );\r | |
187 | \r | |
188 | /**\r | |
189 | Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r | |
190 | \r | |
191 | This function returns after the IPI has been accepted by the target processor.\r | |
192 | \r | |
193 | if StartupRoutine >= 1M, then ASSERT.\r | |
194 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
195 | \r | |
196 | @param ApicId Specify the local APIC ID of the target processor.\r | |
197 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
198 | address and 4K aligned.\r | |
199 | **/\r | |
200 | VOID\r | |
201 | EFIAPI\r | |
202 | SendInitSipiSipi (\r | |
203 | IN UINT32 ApicId,\r | |
204 | IN UINT32 StartupRoutine\r | |
205 | );\r | |
206 | \r | |
207 | /**\r | |
208 | Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r | |
209 | \r | |
210 | This function returns after the IPI has been accepted by the target processors.\r | |
211 | \r | |
212 | if StartupRoutine >= 1M, then ASSERT.\r | |
213 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
214 | \r | |
215 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
216 | address and 4K aligned.\r | |
217 | **/\r | |
218 | VOID\r | |
219 | EFIAPI\r | |
220 | SendInitSipiSipiAllExcludingSelf (\r | |
221 | IN UINT32 StartupRoutine\r | |
222 | );\r | |
223 | \r | |
224 | /**\r | |
225 | Initialize the state of the SoftwareEnable bit in the Local APIC\r | |
226 | Spurious Interrupt Vector register.\r | |
227 | \r | |
228 | @param Enable If TRUE, then set SoftwareEnable to 1\r | |
229 | If FALSE, then set SoftwareEnable to 0.\r | |
230 | \r | |
231 | **/\r | |
232 | VOID\r | |
233 | EFIAPI\r | |
234 | InitializeLocalApicSoftwareEnable (\r | |
235 | IN BOOLEAN Enable\r | |
236 | );\r | |
237 | \r | |
238 | /**\r | |
239 | Programming Virtual Wire Mode.\r | |
240 | \r | |
241 | This function programs the local APIC for virtual wire mode following\r | |
242 | the example described in chapter A.3 of the MP 1.4 spec.\r | |
243 | \r | |
244 | IOxAPIC is not involved in this type of virtual wire mode.\r | |
245 | **/\r | |
246 | VOID\r | |
247 | EFIAPI\r | |
248 | ProgramVirtualWireMode (\r | |
249 | VOID\r | |
250 | );\r | |
251 | \r | |
252 | /**\r | |
253 | Disable LINT0 & LINT1 interrupts.\r | |
254 | \r | |
255 | This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r | |
256 | **/\r | |
257 | VOID\r | |
258 | EFIAPI\r | |
259 | DisableLvtInterrupts (\r | |
260 | VOID\r | |
261 | );\r | |
262 | \r | |
263 | /**\r | |
264 | Read the initial count value from the init-count register.\r | |
265 | \r | |
266 | @return The initial count value read from the init-count register.\r | |
267 | **/\r | |
268 | UINT32\r | |
269 | EFIAPI\r | |
270 | GetApicTimerInitCount (\r | |
271 | VOID\r | |
272 | );\r | |
273 | \r | |
274 | /**\r | |
275 | Read the current count value from the current-count register.\r | |
276 | \r | |
277 | @return The current count value read from the current-count register.\r | |
278 | **/\r | |
279 | UINT32\r | |
280 | EFIAPI\r | |
281 | GetApicTimerCurrentCount (\r | |
282 | VOID\r | |
283 | );\r | |
284 | \r | |
285 | /**\r | |
286 | Initialize the local APIC timer.\r | |
287 | \r | |
288 | The local APIC timer is initialized and enabled.\r | |
289 | \r | |
290 | @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
291 | If it is 0, then use the current divide value in the DCR.\r | |
292 | @param InitCount The initial count value.\r | |
293 | @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
294 | @param Vector The timer interrupt vector number.\r | |
295 | **/\r | |
296 | VOID\r | |
297 | EFIAPI\r | |
298 | InitializeApicTimer (\r | |
299 | IN UINTN DivideValue,\r | |
300 | IN UINT32 InitCount,\r | |
301 | IN BOOLEAN PeriodicMode,\r | |
302 | IN UINT8 Vector\r | |
303 | );\r | |
304 | \r | |
305 | /**\r | |
306 | Get the state of the local APIC timer.\r | |
307 | \r | |
308 | @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
309 | @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
310 | @param Vector Return the timer interrupt vector number.\r | |
311 | **/\r | |
312 | VOID\r | |
313 | EFIAPI\r | |
314 | GetApicTimerState (\r | |
315 | OUT UINTN *DivideValue OPTIONAL,\r | |
316 | OUT BOOLEAN *PeriodicMode OPTIONAL,\r | |
317 | OUT UINT8 *Vector OPTIONAL\r | |
318 | );\r | |
319 | \r | |
320 | /**\r | |
321 | Enable the local APIC timer interrupt.\r | |
322 | **/\r | |
323 | VOID\r | |
324 | EFIAPI\r | |
325 | EnableApicTimerInterrupt (\r | |
326 | VOID\r | |
327 | );\r | |
328 | \r | |
329 | /**\r | |
330 | Disable the local APIC timer interrupt.\r | |
331 | **/\r | |
332 | VOID\r | |
333 | EFIAPI\r | |
334 | DisableApicTimerInterrupt (\r | |
335 | VOID\r | |
336 | );\r | |
337 | \r | |
338 | /**\r | |
339 | Get the local APIC timer interrupt state.\r | |
340 | \r | |
341 | @retval TRUE The local APIC timer interrupt is enabled.\r | |
342 | @retval FALSE The local APIC timer interrupt is disabled.\r | |
343 | **/\r | |
344 | BOOLEAN\r | |
345 | EFIAPI\r | |
346 | GetApicTimerInterruptState (\r | |
347 | VOID\r | |
348 | );\r | |
349 | \r | |
350 | /**\r | |
351 | Send EOI to the local APIC.\r | |
352 | **/\r | |
353 | VOID\r | |
354 | EFIAPI\r | |
355 | SendApicEoi (\r | |
356 | VOID\r | |
357 | );\r | |
358 | \r | |
359 | /**\r | |
360 | Get the 32-bit address that a device should use to send a Message Signaled\r | |
361 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r | |
362 | \r | |
363 | @return 32-bit address used to send an MSI to the Local APIC.\r | |
364 | **/\r | |
365 | UINT32\r | |
366 | EFIAPI\r | |
367 | GetApicMsiAddress (\r | |
368 | VOID\r | |
369 | );\r | |
370 | \r | |
371 | /**\r | |
372 | Get the 64-bit data value that a device should use to send a Message Signaled\r | |
373 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r | |
374 | \r | |
375 | If Vector is not in range 0x10..0xFE, then ASSERT().\r | |
376 | If DeliveryMode is not supported, then ASSERT().\r | |
377 | \r | |
378 | @param Vector The 8-bit interrupt vector associated with the MSI.\r | |
379 | Must be in the range 0x10..0xFE\r | |
380 | @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r | |
381 | is handled. The only supported values are:\r | |
382 | 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r | |
383 | 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
384 | 2: LOCAL_APIC_DELIVERY_MODE_SMI\r | |
385 | 4: LOCAL_APIC_DELIVERY_MODE_NMI\r | |
386 | 5: LOCAL_APIC_DELIVERY_MODE_INIT\r | |
387 | 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r | |
388 | \r | |
389 | @param LevelTriggered TRUE specifies a level triggered interrupt.\r | |
390 | FALSE specifies an edge triggered interrupt.\r | |
391 | @param AssertionLevel Ignored if LevelTriggered is FALSE.\r | |
392 | TRUE specifies a level triggered interrupt that active\r | |
393 | when the interrupt line is asserted.\r | |
394 | FALSE specifies a level triggered interrupt that active\r | |
395 | when the interrupt line is deasserted.\r | |
396 | \r | |
397 | @return 64-bit data value used to send an MSI to the Local APIC.\r | |
398 | **/\r | |
399 | UINT64\r | |
400 | EFIAPI\r | |
401 | GetApicMsiValue (\r | |
402 | IN UINT8 Vector,\r | |
403 | IN UINTN DeliveryMode,\r | |
404 | IN BOOLEAN LevelTriggered,\r | |
405 | IN BOOLEAN AssertionLevel\r | |
406 | );\r | |
407 | \r | |
408 | /**\r | |
409 | Get Package ID/Core ID/Thread ID of a processor.\r | |
410 | \r | |
411 | The algorithm assumes the target system has symmetry across physical\r | |
412 | package boundaries with respect to the number of logical processors\r | |
413 | per package, number of cores per package.\r | |
414 | \r | |
415 | @param[in] InitialApicId Initial APIC ID of the target logical processor.\r | |
416 | @param[out] Package Returns the processor package ID.\r | |
417 | @param[out] Core Returns the processor core ID.\r | |
418 | @param[out] Thread Returns the processor thread ID.\r | |
419 | **/\r | |
420 | VOID\r | |
421 | EFIAPI\r | |
422 | GetProcessorLocationByApicId (\r | |
423 | IN UINT32 InitialApicId,\r | |
424 | OUT UINT32 *Package OPTIONAL,\r | |
425 | OUT UINT32 *Core OPTIONAL,\r | |
426 | OUT UINT32 *Thread OPTIONAL\r | |
427 | );\r | |
428 | \r | |
429 | /**\r | |
430 | Get Package ID/Module ID/Tile ID/Die ID/Core ID/Thread ID of a processor.\r | |
431 | \r | |
432 | The algorithm assumes the target system has symmetry across physical\r | |
433 | package boundaries with respect to the number of threads per core, number of\r | |
434 | cores per module, number of modules per tile, number of tiles per die, number\r | |
435 | of dies per package.\r | |
436 | \r | |
437 | @param[in] InitialApicId Initial APIC ID of the target logical processor.\r | |
438 | @param[out] Package Returns the processor package ID.\r | |
439 | @param[out] Die Returns the processor die ID.\r | |
440 | @param[out] Tile Returns the processor tile ID.\r | |
441 | @param[out] Module Returns the processor module ID.\r | |
442 | @param[out] Core Returns the processor core ID.\r | |
443 | @param[out] Thread Returns the processor thread ID.\r | |
444 | **/\r | |
445 | VOID\r | |
446 | EFIAPI\r | |
447 | GetProcessorLocation2ByApicId (\r | |
448 | IN UINT32 InitialApicId,\r | |
449 | OUT UINT32 *Package OPTIONAL,\r | |
450 | OUT UINT32 *Die OPTIONAL,\r | |
451 | OUT UINT32 *Tile OPTIONAL,\r | |
452 | OUT UINT32 *Module OPTIONAL,\r | |
453 | OUT UINT32 *Core OPTIONAL,\r | |
454 | OUT UINT32 *Thread OPTIONAL\r | |
455 | );\r | |
456 | \r | |
457 | #endif\r |