[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / BroadwellMsr.h

/** @file\r
  MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.13.\r
\r
**/\r
\r
#ifndef __BROADWELL_MSR_H__\r
#define __BROADWELL_MSR_H__\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
  Is Intel processors based on the Broadwell microarchitecture?\r
\r
  @param   DisplayFamily  Display Family ID\r
  @param   DisplayModel   Display Model ID\r
\r
  @retval  TRUE   Yes, it is.\r
  @retval  FALSE  No, it isn't.\r
**/\r
#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
  (DisplayFamily == 0x06 && \\r
   (                        \\r
    DisplayModel == 0x3D || \\r
    DisplayModel == 0x47 || \\r
    DisplayModel == 0x4F || \\r
    DisplayModel == 0x56    \\r
    )                       \\r
   )\r
\r
/**\r
  Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
  Facilities.".\r
\r
  @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r
  AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
  @endcode\r
  @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS    0x0000038E\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Ovf_PMC0.\r
    ///\r
    UINT32  Ovf_PMC0:1;\r
    ///\r
    /// [Bit 1] Ovf_PMC1.\r
    ///\r
    UINT32  Ovf_PMC1:1;\r
    ///\r
    /// [Bit 2] Ovf_PMC2.\r
    ///\r
    UINT32  Ovf_PMC2:1;\r
    ///\r
    /// [Bit 3] Ovf_PMC3.\r
    ///\r
    UINT32  Ovf_PMC3:1;\r
    UINT32  Reserved1:28;\r
    ///\r
    /// [Bit 32] Ovf_FixedCtr0.\r
    ///\r
    UINT32  Ovf_FixedCtr0:1;\r
    ///\r
    /// [Bit 33] Ovf_FixedCtr1.\r
    ///\r
    UINT32  Ovf_FixedCtr1:1;\r
    ///\r
    /// [Bit 34] Ovf_FixedCtr2.\r
    ///\r
    UINT32  Ovf_FixedCtr2:1;\r
    UINT32  Reserved2:20;\r
    ///\r
    /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
    /// Addresses (ToPA).".\r
    ///\r
    UINT32  Trace_ToPA_PMI:1;\r
    UINT32  Reserved3:5;\r
    ///\r
    /// [Bit 61] Ovf_Uncore.\r
    ///\r
    UINT32  Ovf_Uncore:1;\r
    ///\r
    /// [Bit 62] Ovf_BufDSSAVE.\r
    ///\r
    UINT32  OvfBuf:1;\r
    ///\r
    /// [Bit 63] CondChgd.\r
    ///\r
    UINT32  CondChgd:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
\r
/**\r
  Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
  specific C-state code names, unrelated to MWAIT extension C-state parameters\r
  or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
\r
  @param  ECX  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r
  AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
  @endcode\r
  @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL     0x000000E2\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
    /// processor-specific C-state code name (consuming the least power) for\r
    /// the package. The default is set as factory-configured package C-state\r
    /// limit. The following C-state code name encodings are supported: 0000b:\r
    /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
    /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r
    ///\r
    UINT32  Limit:4;\r
    UINT32  Reserved1:6;\r
    ///\r
    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
    ///\r
    UINT32  IO_MWAIT:1;\r
    UINT32  Reserved2:4;\r
    ///\r
    /// [Bit 15] CFG Lock (R/WO).\r
    ///\r
    UINT32  CFGLock:1;\r
    UINT32  Reserved3:9;\r
    ///\r
    /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
    ///\r
    UINT32  C3AutoDemotion:1;\r
    ///\r
    /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
    ///\r
    UINT32  C1AutoDemotion:1;\r
    ///\r
    /// [Bit 27] Enable C3 Undemotion (R/W).\r
    ///\r
    UINT32  C3Undemotion:1;\r
    ///\r
    /// [Bit 28] Enable C1 Undemotion (R/W).\r
    ///\r
    UINT32  C1Undemotion:1;\r
    ///\r
    /// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r
    ///\r
    UINT32  CStateAutoDemotion:1;\r
    ///\r
    /// [Bit 30] Enable Package C-State Undemotion (R/W).\r
    ///\r
    UINT32  CStateUndemotion:1;\r
    UINT32  Reserved4:1;\r
    UINT32  Reserved5:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
\r
/**\r
  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
  RW if MSR_PLATFORM_INFO.[28] = 1.\r
\r
  @param  ECX  MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r
  @endcode\r
  @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_BROADWELL_TURBO_RATIO_LIMIT          0x000001AD\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
    /// limit of 1 core active.\r
    ///\r
    UINT32  Maximum1C:8;\r
    ///\r
    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
    /// limit of 2 core active.\r
    ///\r
    UINT32  Maximum2C:8;\r
    ///\r
    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
    /// limit of 3 core active.\r
    ///\r
    UINT32  Maximum3C:8;\r
    ///\r
    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
    /// limit of 4 core active.\r
    ///\r
    UINT32  Maximum4C:8;\r
    ///\r
    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
    /// limit of 5core active.\r
    ///\r
    UINT32  Maximum5C:8;\r
    ///\r
    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
    /// limit of 6core active.\r
    ///\r
    UINT32  Maximum6C:8;\r
    UINT32  Reserved:16;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
\r
\r
/**\r
  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL\r
  Domains.".\r
\r
  @param  ECX  MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r
  @endcode\r
  @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_BROADWELL_PP0_ENERGY_STATUS          0x00000639\r
\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r
	3	\r
	4	Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
	5	are provided for MSRs that contain one or more bit fields. If the MSR value\r
	6	returned is a single 32-bit or 64-bit value, then a data structure is not\r
	7	provided for that MSR.\r
	8	\r
	9	Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
	10	This program and the accompanying materials\r
	11	are licensed and made available under the terms and conditions of the BSD License\r
	12	which accompanies this distribution. The full text of the license may be found at\r
	13	http://opensource.org/licenses/bsd-license.php\r
	14	\r
	15	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	16	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	17	\r
	18	@par Specification Reference:\r
	19	Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
	20	September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.13.\r
	21	\r
	22	**/\r
	23	\r
	24	#ifndef __BROADWELL_MSR_H__\r
	25	#define __BROADWELL_MSR_H__\r
	26	\r
	27	#include <Register/ArchitecturalMsr.h>\r
	28	\r
	29	/**\r
	30	Is Intel processors based on the Broadwell microarchitecture?\r
	31	\r
	32	@param DisplayFamily Display Family ID\r
	33	@param DisplayModel Display Model ID\r
	34	\r
	35	@retval TRUE Yes, it is.\r
	36	@retval FALSE No, it isn't.\r
	37	**/\r
	38	#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
	39	(DisplayFamily == 0x06 && \\r
	40	( \\r
	41	DisplayModel == 0x3D \|\| \\r
	42	DisplayModel == 0x47 \|\| \\r
	43	DisplayModel == 0x4F \|\| \\r
	44	DisplayModel == 0x56 \\r
	45	) \\r
	46	)\r
	47	\r
	48	/**\r
	49	Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
	50	Facilities.".\r
	51	\r
	52	@param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
	53	@param EAX Lower 32-bits of MSR value.\r
	54	Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
	55	@param EDX Upper 32-bits of MSR value.\r
	56	Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
	57	\r
	58	<b>Example usage</b>\r
	59	@code\r
	60	MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
	61	\r
	62	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r
	63	AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
	64	@endcode\r
	65	@note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
	66	**/\r
	67	#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
	68	\r
	69	/**\r
	70	MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
	71	**/\r
	72	typedef union {\r
	73	///\r
	74	/// Individual bit fields\r
	75	///\r
	76	struct {\r
	77	///\r
	78	/// [Bit 0] Ovf_PMC0.\r
	79	///\r
	80	UINT32 Ovf_PMC0:1;\r
	81	///\r
	82	/// [Bit 1] Ovf_PMC1.\r
	83	///\r
	84	UINT32 Ovf_PMC1:1;\r
	85	///\r
	86	/// [Bit 2] Ovf_PMC2.\r
	87	///\r
	88	UINT32 Ovf_PMC2:1;\r
	89	///\r
	90	/// [Bit 3] Ovf_PMC3.\r
	91	///\r
	92	UINT32 Ovf_PMC3:1;\r
	93	UINT32 Reserved1:28;\r
	94	///\r
	95	/// [Bit 32] Ovf_FixedCtr0.\r
	96	///\r
	97	UINT32 Ovf_FixedCtr0:1;\r
	98	///\r
	99	/// [Bit 33] Ovf_FixedCtr1.\r
	100	///\r
	101	UINT32 Ovf_FixedCtr1:1;\r
	102	///\r
	103	/// [Bit 34] Ovf_FixedCtr2.\r
	104	///\r
	105	UINT32 Ovf_FixedCtr2:1;\r
	106	UINT32 Reserved2:20;\r
	107	///\r
	108	/// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
	109	/// Addresses (ToPA).".\r
	110	///\r
	111	UINT32 Trace_ToPA_PMI:1;\r
	112	UINT32 Reserved3:5;\r
	113	///\r
	114	/// [Bit 61] Ovf_Uncore.\r
	115	///\r
	116	UINT32 Ovf_Uncore:1;\r
	117	///\r
	118	/// [Bit 62] Ovf_BufDSSAVE.\r
	119	///\r
	120	UINT32 OvfBuf:1;\r
	121	///\r
	122	/// [Bit 63] CondChgd.\r
	123	///\r
	124	UINT32 CondChgd:1;\r
	125	} Bits;\r
	126	///\r
	127	/// All bit fields as a 64-bit value\r
	128	///\r
	129	UINT64 Uint64;\r
	130	} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
	131	\r
	132	\r
	133	/**\r
	134	Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
	135	specific C-state code names, unrelated to MWAIT extension C-state parameters\r
	136	or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
	137	\r
	138	@param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
	139	@param EAX Lower 32-bits of MSR value.\r
	140	Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
	141	@param EDX Upper 32-bits of MSR value.\r
	142	Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
	143	\r
	144	<b>Example usage</b>\r
	145	@code\r
	146	MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
	147	\r
	148	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r
	149	AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
	150	@endcode\r
	151	@note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
	152	**/\r
	153	#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
	154	\r
	155	/**\r
	156	MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r
	157	**/\r
	158	typedef union {\r
	159	///\r
	160	/// Individual bit fields\r
	161	///\r
	162	struct {\r
	163	///\r
	164	/// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
	165	/// processor-specific C-state code name (consuming the least power) for\r
	166	/// the package. The default is set as factory-configured package C-state\r
	167	/// limit. The following C-state code name encodings are supported: 0000b:\r
	168	/// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
	169	/// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r
	170	///\r
	171	UINT32 Limit:4;\r
	172	UINT32 Reserved1:6;\r
	173	///\r
	174	/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
	175	///\r
	176	UINT32 IO_MWAIT:1;\r
	177	UINT32 Reserved2:4;\r
	178	///\r
	179	/// [Bit 15] CFG Lock (R/WO).\r
	180	///\r
	181	UINT32 CFGLock:1;\r
	182	UINT32 Reserved3:9;\r
	183	///\r
	184	/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
	185	///\r
	186	UINT32 C3AutoDemotion:1;\r
	187	///\r
	188	/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
	189	///\r
	190	UINT32 C1AutoDemotion:1;\r
	191	///\r
	192	/// [Bit 27] Enable C3 Undemotion (R/W).\r
	193	///\r
	194	UINT32 C3Undemotion:1;\r
	195	///\r
	196	/// [Bit 28] Enable C1 Undemotion (R/W).\r
	197	///\r
	198	UINT32 C1Undemotion:1;\r
	199	///\r
	200	/// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r
	201	///\r
	202	UINT32 CStateAutoDemotion:1;\r
	203	///\r
	204	/// [Bit 30] Enable Package C-State Undemotion (R/W).\r
	205	///\r
	206	UINT32 CStateUndemotion:1;\r
	207	UINT32 Reserved4:1;\r
	208	UINT32 Reserved5:32;\r
	209	} Bits;\r
	210	///\r
	211	/// All bit fields as a 32-bit value\r
	212	///\r
	213	UINT32 Uint32;\r
	214	///\r
	215	/// All bit fields as a 64-bit value\r
	216	///\r
	217	UINT64 Uint64;\r
	218	} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
	219	\r
	220	\r
	221	/**\r
	222	Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
	223	RW if MSR_PLATFORM_INFO.[28] = 1.\r
	224	\r
	225	@param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
	226	@param EAX Lower 32-bits of MSR value.\r
	227	Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
	228	@param EDX Upper 32-bits of MSR value.\r
	229	Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
	230	\r
	231	<b>Example usage</b>\r
	232	@code\r
	233	MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r
	234	\r
	235	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r
	236	@endcode\r
	237	@note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
	238	**/\r
	239	#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r
	240	\r
	241	/**\r
	242	MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r
	243	**/\r
	244	typedef union {\r
	245	///\r
	246	/// Individual bit fields\r
	247	///\r
	248	struct {\r
	249	///\r
	250	/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
	251	/// limit of 1 core active.\r
	252	///\r
	253	UINT32 Maximum1C:8;\r
	254	///\r
	255	/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
	256	/// limit of 2 core active.\r
	257	///\r
	258	UINT32 Maximum2C:8;\r
	259	///\r
	260	/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
	261	/// limit of 3 core active.\r
	262	///\r
	263	UINT32 Maximum3C:8;\r
	264	///\r
	265	/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
	266	/// limit of 4 core active.\r
	267	///\r
	268	UINT32 Maximum4C:8;\r
	269	///\r
	270	/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
	271	/// limit of 5core active.\r
	272	///\r
	273	UINT32 Maximum5C:8;\r
	274	///\r
	275	/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
	276	/// limit of 6core active.\r
	277	///\r
	278	UINT32 Maximum6C:8;\r
	279	UINT32 Reserved:16;\r
	280	} Bits;\r
	281	///\r
	282	/// All bit fields as a 64-bit value\r
	283	///\r
	284	UINT64 Uint64;\r
	285	} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
	286	\r
	287	\r
	288	/**\r
	289	Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
	290	Domains.".\r
	291	\r
	292	@param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r
	293	@param EAX Lower 32-bits of MSR value.\r
	294	@param EDX Upper 32-bits of MSR value.\r
	295	\r
	296	<b>Example usage</b>\r
	297	@code\r
	298	UINT64 Msr;\r
	299	\r
	300	Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r
	301	@endcode\r
	302	@note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
	303	**/\r
	304	#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639\r
	305	\r
	306	#endif\r