[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / Xeon5600Msr.h

/** @file\r
  MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.7.\r
\r
**/\r
\r
#ifndef __XEON_5600_MSR_H__\r
#define __XEON_5600_MSR_H__\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
  Is Intel(R) Xeon(R) Processor Series 5600?\r
\r
  @param   DisplayFamily  Display Family ID\r
  @param   DisplayModel   Display Model ID\r
\r
  @retval  TRUE   Yes, it is.\r
  @retval  FALSE  No, it isn't.\r
**/\r
#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \\r
  (DisplayFamily == 0x06 && \\r
   (                        \\r
    DisplayModel == 0x25 || \\r
    DisplayModel == 0x2C    \\r
    )                       \\r
   )\r
\r
/**\r
  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
  handler to handle unsuccessful read of this MSR.\r
\r
  @param  ECX  MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);\r
  AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);\r
  @endcode\r
  @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
#define MSR_XEON_5600_FEATURE_CONFIG             0x0000013C\r
\r
/**\r
  MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this\r
    /// MSR, the configuration of AES instruction set availability is as\r
    /// follows: 11b: AES instructions are not available until next RESET.\r
    /// otherwise, AES instructions are available. Note, AES instruction set\r
    /// is not available if read is unsuccessful. If the configuration is not\r
    /// 01b, AES instruction can be mis-configured if a privileged agent\r
    /// unintentionally writes 11b.\r
    ///\r
    UINT32  AESConfiguration:2;\r
    UINT32  Reserved1:30;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;\r
\r
\r
/**\r
  Thread. Offcore Response Event Select Register (R/W).\r
\r
  @param  ECX  MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);\r
  AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);\r
  @endcode\r
  @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
#define MSR_XEON_5600_OFFCORE_RSP_1              0x000001A7\r
\r
\r
/**\r
  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
  RW if MSR_PLATFORM_INFO.[28] = 1.\r
\r
  @param  ECX  MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);\r
  @endcode\r
  @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_XEON_5600_TURBO_RATIO_LIMIT          0x000001AD\r
\r
/**\r
  MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
    /// limit of 1 core active.\r
    ///\r
    UINT32  Maximum1C:8;\r
    ///\r
    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
    /// limit of 2 core active.\r
    ///\r
    UINT32  Maximum2C:8;\r
    ///\r
    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
    /// limit of 3 core active.\r
    ///\r
    UINT32  Maximum3C:8;\r
    ///\r
    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
    /// limit of 4 core active.\r
    ///\r
    UINT32  Maximum4C:8;\r
    ///\r
    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
    /// limit of 5 core active.\r
    ///\r
    UINT32  Maximum5C:8;\r
    ///\r
    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
    /// limit of 6 core active.\r
    ///\r
    UINT32  Maximum6C:8;\r
    UINT32  Reserved:16;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;\r
\r
\r
/**\r
  Package. See Table 35-2.\r
\r
  @param  ECX  MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);\r
  AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);\r
  @endcode\r
  @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
**/\r
#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS      0x000001B0\r
\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.\r
	3	\r
	4	Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
	5	are provided for MSRs that contain one or more bit fields. If the MSR value\r
	6	returned is a single 32-bit or 64-bit value, then a data structure is not\r
	7	provided for that MSR.\r
	8	\r
	9	Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
	10	This program and the accompanying materials\r
	11	are licensed and made available under the terms and conditions of the BSD License\r
	12	which accompanies this distribution. The full text of the license may be found at\r
	13	http://opensource.org/licenses/bsd-license.php\r
	14	\r
	15	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	16	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	17	\r
	18	@par Specification Reference:\r
	19	Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
	20	September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.7.\r
	21	\r
	22	**/\r
	23	\r
	24	#ifndef __XEON_5600_MSR_H__\r
	25	#define __XEON_5600_MSR_H__\r
	26	\r
	27	#include <Register/ArchitecturalMsr.h>\r
	28	\r
	29	/**\r
	30	Is Intel(R) Xeon(R) Processor Series 5600?\r
	31	\r
	32	@param DisplayFamily Display Family ID\r
	33	@param DisplayModel Display Model ID\r
	34	\r
	35	@retval TRUE Yes, it is.\r
	36	@retval FALSE No, it isn't.\r
	37	**/\r
	38	#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \\r
	39	(DisplayFamily == 0x06 && \\r
	40	( \\r
	41	DisplayModel == 0x25 \|\| \\r
	42	DisplayModel == 0x2C \\r
	43	) \\r
	44	)\r
	45	\r
	46	/**\r
	47	Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
	48	handler to handle unsuccessful read of this MSR.\r
	49	\r
	50	@param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)\r
	51	@param EAX Lower 32-bits of MSR value.\r
	52	Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
	53	@param EDX Upper 32-bits of MSR value.\r
	54	Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
	55	\r
	56	<b>Example usage</b>\r
	57	@code\r
	58	MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;\r
	59	\r
	60	Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);\r
	61	AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);\r
	62	@endcode\r
	63	@note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
	64	**/\r
	65	#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C\r
	66	\r
	67	/**\r
	68	MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG\r
	69	**/\r
	70	typedef union {\r
	71	///\r
	72	/// Individual bit fields\r
	73	///\r
	74	struct {\r
	75	///\r
	76	/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
	77	/// MSR, the configuration of AES instruction set availability is as\r
	78	/// follows: 11b: AES instructions are not available until next RESET.\r
	79	/// otherwise, AES instructions are available. Note, AES instruction set\r
	80	/// is not available if read is unsuccessful. If the configuration is not\r
	81	/// 01b, AES instruction can be mis-configured if a privileged agent\r
	82	/// unintentionally writes 11b.\r
	83	///\r
	84	UINT32 AESConfiguration:2;\r
	85	UINT32 Reserved1:30;\r
	86	UINT32 Reserved2:32;\r
	87	} Bits;\r
	88	///\r
	89	/// All bit fields as a 32-bit value\r
	90	///\r
	91	UINT32 Uint32;\r
	92	///\r
	93	/// All bit fields as a 64-bit value\r
	94	///\r
	95	UINT64 Uint64;\r
	96	} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;\r
	97	\r
	98	\r
	99	/**\r
	100	Thread. Offcore Response Event Select Register (R/W).\r
	101	\r
	102	@param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)\r
	103	@param EAX Lower 32-bits of MSR value.\r
	104	@param EDX Upper 32-bits of MSR value.\r
	105	\r
	106	<b>Example usage</b>\r
	107	@code\r
	108	UINT64 Msr;\r
	109	\r
	110	Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);\r
	111	AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);\r
	112	@endcode\r
	113	@note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
	114	**/\r
	115	#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7\r
	116	\r
	117	\r
	118	/**\r
	119	Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
	120	RW if MSR_PLATFORM_INFO.[28] = 1.\r
	121	\r
	122	@param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)\r
	123	@param EAX Lower 32-bits of MSR value.\r
	124	Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
	125	@param EDX Upper 32-bits of MSR value.\r
	126	Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
	127	\r
	128	<b>Example usage</b>\r
	129	@code\r
	130	MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;\r
	131	\r
	132	Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);\r
	133	@endcode\r
	134	@note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
	135	**/\r
	136	#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD\r
	137	\r
	138	/**\r
	139	MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER\r
	140	**/\r
	141	typedef union {\r
	142	///\r
	143	/// Individual bit fields\r
	144	///\r
	145	struct {\r
	146	///\r
	147	/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
	148	/// limit of 1 core active.\r
	149	///\r
	150	UINT32 Maximum1C:8;\r
	151	///\r
	152	/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
	153	/// limit of 2 core active.\r
	154	///\r
	155	UINT32 Maximum2C:8;\r
	156	///\r
	157	/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
	158	/// limit of 3 core active.\r
	159	///\r
	160	UINT32 Maximum3C:8;\r
	161	///\r
	162	/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
	163	/// limit of 4 core active.\r
	164	///\r
	165	UINT32 Maximum4C:8;\r
	166	///\r
	167	/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
	168	/// limit of 5 core active.\r
	169	///\r
	170	UINT32 Maximum5C:8;\r
	171	///\r
	172	/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
	173	/// limit of 6 core active.\r
	174	///\r
	175	UINT32 Maximum6C:8;\r
	176	UINT32 Reserved:16;\r
	177	} Bits;\r
	178	///\r
	179	/// All bit fields as a 64-bit value\r
	180	///\r
	181	UINT64 Uint64;\r
	182	} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;\r
	183	\r
	184	\r
	185	/**\r
	186	Package. See Table 35-2.\r
	187	\r
	188	@param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
	189	@param EAX Lower 32-bits of MSR value.\r
	190	@param EDX Upper 32-bits of MSR value.\r
	191	\r
	192	<b>Example usage</b>\r
	193	@code\r
	194	UINT64 Msr;\r
	195	\r
	196	Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);\r
	197	AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);\r
	198	@endcode\r
	199	@note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
	200	**/\r
	201	#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0\r
	202	\r
	203	#endif\r