[mirror_edk2.git] / UefiCpuPkg / Library / CpuCommonFeaturesLib / Ppin.c

/** @file\r
  Protected Processor Inventory Number(PPIN) feature.\r
\r
  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "CpuCommonFeatures.h"\r
\r
/**\r
  Prepares for the data used by CPU feature detection and initialization.\r
\r
  @param[in]  NumberOfProcessors  The number of CPUs in the platform.\r
\r
  @return  Pointer to a buffer of CPU related configuration data.\r
\r
  @note This service could be called by BSP only.\r
**/\r
VOID *\r
EFIAPI\r
PpinGetConfigData (\r
  IN UINTN  NumberOfProcessors\r
  )\r
{\r
  VOID  *ConfigData;\r
\r
  ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);\r
  ASSERT (ConfigData != NULL);\r
  return ConfigData;\r
}\r
\r
/**\r
  Detects if Protected Processor Inventory Number feature supported on current\r
  processor.\r
\r
  @param[in]  ProcessorNumber  The index of the CPU executing this function.\r
  @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
                               structure for the CPU executing this function.\r
  @param[in]  ConfigData       A pointer to the configuration buffer returned\r
                               by CPU_FEATURE_GET_CONFIG_DATA.  NULL if\r
                               CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
                               RegisterCpuFeature().\r
\r
  @retval TRUE     Protected Processor Inventory Number feature is supported.\r
  @retval FALSE    Protected Processor Inventory Number feature is not supported.\r
\r
  @note This service could be called by BSP/APs.\r
**/\r
BOOLEAN\r
EFIAPI\r
PpinSupport (\r
  IN UINTN                             ProcessorNumber,\r
  IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,\r
  IN VOID                              *ConfigData  OPTIONAL\r
  )\r
{\r
  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  PlatformInfo;\r
  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER         *MsrPpinCtrl;\r
\r
  if ((CpuInfo->DisplayFamily == 0x06) &&\r
      ((CpuInfo->DisplayModel == 0x3E) ||      // Xeon E5 V2\r
       (CpuInfo->DisplayModel == 0x56) ||      // Xeon Processor D Product\r
       (CpuInfo->DisplayModel == 0x4F) ||      // Xeon E5 v4, E7 v4\r
       (CpuInfo->DisplayModel == 0x55) ||      // Xeon Processor Scalable\r
       (CpuInfo->DisplayModel == 0x57) ||      // Xeon Phi processor 3200, 5200, 7200 series.\r
       (CpuInfo->DisplayModel == 0x85)         // Future Xeon phi processor\r
      ))\r
  {\r
    //\r
    // Check whether platform support this feature.\r
    //\r
    PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
    if (PlatformInfo.Bits.PPIN_CAP != 0) {\r
      MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;\r
      ASSERT (MsrPpinCtrl != NULL);\r
      MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
      return TRUE;\r
    }\r
  }\r
\r
  return FALSE;\r
}\r
\r
/**\r
  Initializes Protected Processor Inventory Number feature to specific state.\r
\r
  @param[in]  ProcessorNumber  The index of the CPU executing this function.\r
  @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
                               structure for the CPU executing this function.\r
  @param[in]  ConfigData       A pointer to the configuration buffer returned\r
                               by CPU_FEATURE_GET_CONFIG_DATA.  NULL if\r
                               CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
                               RegisterCpuFeature().\r
  @param[in]  State            If TRUE, then the Protected Processor Inventory\r
                               Number feature must be enabled.\r
                               If FALSE, then the Protected Processor Inventory\r
                               Number feature must be disabled.\r
\r
  @retval RETURN_SUCCESS       Protected Processor Inventory Number feature is\r
                               initialized.\r
  @retval RETURN_DEVICE_ERROR  Device can't change state because it has been\r
                               locked.\r
\r
  @note This service could be called by BSP only.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PpinInitialize (\r
  IN UINTN                             ProcessorNumber,\r
  IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,\r
  IN VOID                              *ConfigData   OPTIONAL,\r
  IN BOOLEAN                           State\r
  )\r
{\r
  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  *MsrPpinCtrl;\r
\r
  MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;\r
  ASSERT (MsrPpinCtrl != NULL);\r
\r
  //\r
  // Check whether processor already lock this register.\r
  // If already locked, just based on the request state and\r
  // the current state to return the status.\r
  //\r
  if (MsrPpinCtrl[ProcessorNumber].Bits.LockOut != 0) {\r
    return MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;\r
  }\r
\r
  //\r
  // Support function already check the processor which support PPIN feature, so this function not need\r
  // to check the processor again.\r
  //\r
  // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL\r
  // once for each package.\r
  //\r
  if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {\r
    return RETURN_SUCCESS;\r
  }\r
\r
  if (State) {\r
    //\r
    // Enable and Unlock.\r
    // According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.\r
    //\r
    MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;\r
    MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 0;\r
  } else {\r
    //\r
    // Disable and Lock.\r
    // According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.\r
    //\r
    MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;\r
    MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 1;\r
  }\r
\r
  CPU_REGISTER_TABLE_WRITE64 (\r
    ProcessorNumber,\r
    Msr,\r
    MSR_IVY_BRIDGE_PPIN_CTL,\r
    MsrPpinCtrl[ProcessorNumber].Uint64\r
    );\r
\r
  return RETURN_SUCCESS;\r
}\r
Commit	Line	Data
	1	/** @file\r
	2	Protected Processor Inventory Number(PPIN) feature.\r
	3	\r
	4	Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
	6	\r
	7	**/\r
	8	\r
	9	#include "CpuCommonFeatures.h"\r
	10	\r
	11	/**\r
	12	Prepares for the data used by CPU feature detection and initialization.\r
	13	\r
	14	@param[in] NumberOfProcessors The number of CPUs in the platform.\r
	15	\r
	16	@return Pointer to a buffer of CPU related configuration data.\r
	17	\r
	18	@note This service could be called by BSP only.\r
	19	**/\r
	20	VOID *\r
	21	EFIAPI\r
	22	PpinGetConfigData (\r
	23	IN UINTN NumberOfProcessors\r
	24	)\r
	25	{\r
	26	VOID *ConfigData;\r
	27	\r
	28	ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);\r
	29	ASSERT (ConfigData != NULL);\r
	30	return ConfigData;\r
	31	}\r
	32	\r
	33	/**\r
	34	Detects if Protected Processor Inventory Number feature supported on current\r
	35	processor.\r
	36	\r
	37	@param[in] ProcessorNumber The index of the CPU executing this function.\r
	38	@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
	39	structure for the CPU executing this function.\r
	40	@param[in] ConfigData A pointer to the configuration buffer returned\r
	41	by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r
	42	CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
	43	RegisterCpuFeature().\r
	44	\r
	45	@retval TRUE Protected Processor Inventory Number feature is supported.\r
	46	@retval FALSE Protected Processor Inventory Number feature is not supported.\r
	47	\r
	48	@note This service could be called by BSP/APs.\r
	49	**/\r
	50	BOOLEAN\r
	51	EFIAPI\r
	52	PpinSupport (\r
	53	IN UINTN ProcessorNumber,\r
	54	IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r
	55	IN VOID *ConfigData OPTIONAL\r
	56	)\r
	57	{\r
	58	MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;\r
	59	MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;\r
	60	\r
	61	if ((CpuInfo->DisplayFamily == 0x06) &&\r
	62	((CpuInfo->DisplayModel == 0x3E) \|\| // Xeon E5 V2\r
	63	(CpuInfo->DisplayModel == 0x56) \|\| // Xeon Processor D Product\r
	64	(CpuInfo->DisplayModel == 0x4F) \|\| // Xeon E5 v4, E7 v4\r
	65	(CpuInfo->DisplayModel == 0x55) \|\| // Xeon Processor Scalable\r
	66	(CpuInfo->DisplayModel == 0x57) \|\| // Xeon Phi processor 3200, 5200, 7200 series.\r
	67	(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor\r
	68	))\r
	69	{\r
	70	//\r
	71	// Check whether platform support this feature.\r
	72	//\r
	73	PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
	74	if (PlatformInfo.Bits.PPIN_CAP != 0) {\r
	75	MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;\r
	76	ASSERT (MsrPpinCtrl != NULL);\r
	77	MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
	78	return TRUE;\r
	79	}\r
	80	}\r
	81	\r
	82	return FALSE;\r
	83	}\r
	84	\r
	85	/**\r
	86	Initializes Protected Processor Inventory Number feature to specific state.\r
	87	\r
	88	@param[in] ProcessorNumber The index of the CPU executing this function.\r
	89	@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
	90	structure for the CPU executing this function.\r
	91	@param[in] ConfigData A pointer to the configuration buffer returned\r
	92	by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r
	93	CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
	94	RegisterCpuFeature().\r
	95	@param[in] State If TRUE, then the Protected Processor Inventory\r
	96	Number feature must be enabled.\r
	97	If FALSE, then the Protected Processor Inventory\r
	98	Number feature must be disabled.\r
	99	\r
	100	@retval RETURN_SUCCESS Protected Processor Inventory Number feature is\r
	101	initialized.\r
	102	@retval RETURN_DEVICE_ERROR Device can't change state because it has been\r
	103	locked.\r
	104	\r
	105	@note This service could be called by BSP only.\r
	106	**/\r
	107	RETURN_STATUS\r
	108	EFIAPI\r
	109	PpinInitialize (\r
	110	IN UINTN ProcessorNumber,\r
	111	IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r
	112	IN VOID *ConfigData OPTIONAL,\r
	113	IN BOOLEAN State\r
	114	)\r
	115	{\r
	116	MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;\r
	117	\r
	118	MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;\r
	119	ASSERT (MsrPpinCtrl != NULL);\r
	120	\r
	121	//\r
	122	// Check whether processor already lock this register.\r
	123	// If already locked, just based on the request state and\r
	124	// the current state to return the status.\r
	125	//\r
	126	if (MsrPpinCtrl[ProcessorNumber].Bits.LockOut != 0) {\r
	127	return MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;\r
	128	}\r
	129	\r
	130	//\r
	131	// Support function already check the processor which support PPIN feature, so this function not need\r
	132	// to check the processor again.\r
	133	//\r
	134	// The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL\r
	135	// once for each package.\r
	136	//\r
	137	if ((CpuInfo->First.Thread == 0) \|\| (CpuInfo->First.Core == 0)) {\r
	138	return RETURN_SUCCESS;\r
	139	}\r
	140	\r
	141	if (State) {\r
	142	//\r
	143	// Enable and Unlock.\r
	144	// According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.\r
	145	//\r
	146	MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;\r
	147	MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;\r
	148	} else {\r
	149	//\r
	150	// Disable and Lock.\r
	151	// According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.\r
	152	//\r
	153	MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;\r
	154	MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;\r
	155	}\r
	156	\r
	157	CPU_REGISTER_TABLE_WRITE64 (\r
	158	ProcessorNumber,\r
	159	Msr,\r
	160	MSR_IVY_BRIDGE_PPIN_CTL,\r
	161	MsrPpinCtrl[ProcessorNumber].Uint64\r
	162	);\r
	163	\r
	164	return RETURN_SUCCESS;\r
	165	}\r