| | 1 | /** @file\r |
| | 2 | SMM profile internal header file.\r |
| | 3 | \r |
| | 4 | Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| | 5 | Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r |
| | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| | 7 | \r |
| | 8 | **/\r |
| | 9 | \r |
| | 10 | #ifndef _SMM_PROFILE_INTERNAL_H_\r |
| | 11 | #define _SMM_PROFILE_INTERNAL_H_\r |
| | 12 | \r |
| | 13 | #include <Protocol/SmmReadyToLock.h>\r |
| | 14 | #include <Library/UefiRuntimeServicesTableLib.h>\r |
| | 15 | #include <Library/DxeServicesTableLib.h>\r |
| | 16 | #include <Library/CpuLib.h>\r |
| | 17 | #include <Library/UefiCpuLib.h>\r |
| | 18 | #include <IndustryStandard/Acpi.h>\r |
| | 19 | \r |
| | 20 | #include "SmmProfileArch.h"\r |
| | 21 | \r |
| | 22 | //\r |
| | 23 | // Configure the SMM_PROFILE DTS region size\r |
| | 24 | //\r |
| | 25 | #define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M\r |
| | 26 | \r |
| | 27 | #define MAX_PF_PAGE_COUNT 0x2\r |
| | 28 | \r |
| | 29 | #define PEBS_RECORD_NUMBER 0x2\r |
| | 30 | \r |
| | 31 | #define MAX_PF_ENTRY_COUNT 10\r |
| | 32 | \r |
| | 33 | //\r |
| | 34 | // This MACRO just enable unit test for the profile\r |
| | 35 | // Please disable it.\r |
| | 36 | //\r |
| | 37 | \r |
| | 38 | #define IA32_PF_EC_ID (1u << 4)\r |
| | 39 | \r |
| | 40 | #define SMM_PROFILE_NAME L"SmmProfileData"\r |
| | 41 | \r |
| | 42 | //\r |
| | 43 | // CPU generic definition\r |
| | 44 | //\r |
| | 45 | #define CPUID1_EDX_XD_SUPPORT 0x100000\r |
| | 46 | #define MSR_EFER 0xc0000080\r |
| | 47 | #define MSR_EFER_XD 0x800\r |
| | 48 | \r |
| | 49 | #define CPUID1_EDX_BTS_AVAILABLE 0x200000\r |
| | 50 | \r |
| | 51 | #define DR6_SINGLE_STEP 0x4000\r |
| | 52 | #define RFLAG_TF 0x100\r |
| | 53 | \r |
| | 54 | #define MSR_DEBUG_CTL 0x1D9\r |
| | 55 | #define MSR_DEBUG_CTL_LBR 0x1\r |
| | 56 | #define MSR_DEBUG_CTL_TR 0x40\r |
| | 57 | #define MSR_DEBUG_CTL_BTS 0x80\r |
| | 58 | #define MSR_DEBUG_CTL_BTINT 0x100\r |
| | 59 | #define MSR_DS_AREA 0x600\r |
| | 60 | \r |
| | 61 | #define HEAP_GUARD_NONSTOP_MODE \\r |
| | 62 | ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)\r |
| | 63 | \r |
| | 64 | #define NULL_DETECTION_NONSTOP_MODE \\r |
| | 65 | ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6)\r |
| | 66 | \r |
| | 67 | typedef struct {\r |
| | 68 | EFI_PHYSICAL_ADDRESS Base;\r |
| | 69 | EFI_PHYSICAL_ADDRESS Top;\r |
| | 70 | } MEMORY_RANGE;\r |
| | 71 | \r |
| | 72 | typedef struct {\r |
| | 73 | MEMORY_RANGE Range;\r |
| | 74 | BOOLEAN Present;\r |
| | 75 | BOOLEAN Nx;\r |
| | 76 | } MEMORY_PROTECTION_RANGE;\r |
| | 77 | \r |
| | 78 | typedef struct {\r |
| | 79 | UINT64 HeaderSize;\r |
| | 80 | UINT64 MaxDataEntries;\r |
| | 81 | UINT64 MaxDataSize;\r |
| | 82 | UINT64 CurDataEntries;\r |
| | 83 | UINT64 CurDataSize;\r |
| | 84 | UINT64 TsegStart;\r |
| | 85 | UINT64 TsegSize;\r |
| | 86 | UINT64 NumSmis;\r |
| | 87 | UINT64 NumCpus;\r |
| | 88 | } SMM_PROFILE_HEADER;\r |
| | 89 | \r |
| | 90 | typedef struct {\r |
| | 91 | UINT64 SmiNum;\r |
| | 92 | UINT64 CpuNum;\r |
| | 93 | UINT64 ApicId;\r |
| | 94 | UINT64 ErrorCode;\r |
| | 95 | UINT64 Instruction;\r |
| | 96 | UINT64 Address;\r |
| | 97 | UINT64 SmiCmd;\r |
| | 98 | } SMM_PROFILE_ENTRY;\r |
| | 99 | \r |
| | 100 | extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;\r |
| | 101 | extern UINTN gSmiExceptionHandlers[];\r |
| | 102 | extern BOOLEAN mXdSupported;\r |
| | 103 | X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported;\r |
| | 104 | X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported;\r |
| | 105 | extern UINTN *mPFEntryCount;\r |
| | 106 | extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r |
| | 107 | extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r |
| | 108 | \r |
| | 109 | //\r |
| | 110 | // Internal functions\r |
| | 111 | //\r |
| | 112 | \r |
| | 113 | /**\r |
| | 114 | Update IDT table to replace page fault handler and INT 1 handler.\r |
| | 115 | \r |
| | 116 | **/\r |
| | 117 | VOID\r |
| | 118 | InitIdtr (\r |
| | 119 | VOID\r |
| | 120 | );\r |
| | 121 | \r |
| | 122 | /**\r |
| | 123 | Check if the memory address will be mapped by 4KB-page.\r |
| | 124 | \r |
| | 125 | @param Address The address of Memory.\r |
| | 126 | \r |
| | 127 | **/\r |
| | 128 | BOOLEAN\r |
| | 129 | IsAddressSplit (\r |
| | 130 | IN EFI_PHYSICAL_ADDRESS Address\r |
| | 131 | );\r |
| | 132 | \r |
| | 133 | /**\r |
| | 134 | Check if the memory address will be mapped by 4KB-page.\r |
| | 135 | \r |
| | 136 | @param Address The address of Memory.\r |
| | 137 | @param Nx The flag indicates if the memory is execute-disable.\r |
| | 138 | \r |
| | 139 | **/\r |
| | 140 | BOOLEAN\r |
| | 141 | IsAddressValid (\r |
| | 142 | IN EFI_PHYSICAL_ADDRESS Address,\r |
| | 143 | IN BOOLEAN *Nx\r |
| | 144 | );\r |
| | 145 | \r |
| | 146 | /**\r |
| | 147 | Page Fault handler for SMM use.\r |
| | 148 | \r |
| | 149 | **/\r |
| | 150 | VOID\r |
| | 151 | SmiDefaultPFHandler (\r |
| | 152 | VOID\r |
| | 153 | );\r |
| | 154 | \r |
| | 155 | /**\r |
| | 156 | Clear TF in FLAGS.\r |
| | 157 | \r |
| | 158 | @param SystemContext A pointer to the processor context when\r |
| | 159 | the interrupt occurred on the processor.\r |
| | 160 | \r |
| | 161 | **/\r |
| | 162 | VOID\r |
| | 163 | ClearTrapFlag (\r |
| | 164 | IN OUT EFI_SYSTEM_CONTEXT SystemContext\r |
| | 165 | );\r |
| | 166 | \r |
| | 167 | #endif // _SMM_PROFILE_H_\r |
projects / mirror_edk2.git / blame_incremental