ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
   6 #
   7 #    SPDX-License-Identifier: BSD-2-Clause-Patent
   8 #
   9 #**/
  10
  11 [Defines]
  12   DEC_SPECIFICATION              = 0x00010005
  13   PACKAGE_NAME                   = ArmPkg
  14   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  15   PACKAGE_VERSION                = 0.1
  16
  17 ################################################################################
  18 #
  19 # Include Section - list of Include Paths that are provided by this package.
  20 #                   Comments are used for Keywords and Module Types.
  21 #
  22 # Supported Module Types:
  23 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  24 #
  25 ################################################################################
  26 [Includes.common]
  27   Include                        # Root include for the package
  28
  29 [LibraryClasses.common]
  30   ArmLib|Include/Library/ArmLib.h
  31   ArmMmuLib|Include/Library/ArmMmuLib.h
  32   SemihostLib|Include/Library/SemihostLib.h
  33   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  34   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  35   ArmGicArchLib|Include/Library/ArmGicArchLib.h
  36   ArmMtlLib|Include/Library/ArmMtlLib.h
  37   ArmSvcLib|Include/Library/ArmSvcLib.h
  38   OpteeLib|Include/Library/OpteeLib.h
  39   StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
  40   ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
  41   ArmGicLib|Include/Library/ArmGicLib.h
  42   ArmHvcLib|Include/Library/ArmHvcLib.h
  43   OemMiscLib|Include/Library/OemMiscLib.h
  44   ArmSmcLib|Include/Library/ArmSmcLib.h
  45
  46
  47 [Guids.common]
  48   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  49
  50   ## ARM MPCore table
  51   # Include/Guid/ArmMpCoreInfo.h
  52   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
  53
  54 [Protocols.common]
  55   ## Arm System Control and Management Interface(SCMI) Base protocol
  56   ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
  57   gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
  58
  59   ## Arm System Control and Management Interface(SCMI) Clock management protocol
  60   ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
  61   gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
  62   gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
  63
  64   ## Arm System Control and Management Interface(SCMI) Clock management protocol
  65   ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
  66   gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
  67
  68 [Ppis]
  69   ## Include/Ppi/ArmMpCoreInfo.h
  70   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
  71
  72 [PcdsFeatureFlag.common]
  73   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
  74
  75   # On ARM Architecture with the Security Extension, the address for the
  76   # Vector Table can be mapped anywhere in the memory map. It means we can
  77   # point the Exception Vector Table to its location in CpuDxe.
  78   # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)
  79   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
  80   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
  81   # it has been configured by the CPU DXE
  82   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
  83
  84   # Define if the GICv3 controller should use the GICv2 legacy
  85   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
  86
  87 [PcdsFeatureFlag.ARM]
  88   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
  89   # TRUE may be appropriate to fix performance problems if you don't care about
  90   # hardware coherency (i.e., no virtualization or cache coherent DMA)
  91   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
  92
  93 [PcdsFeatureFlag.AARCH64]
  94   ## Used to select method for requesting services from S-EL1.<BR><BR>
  95   #   TRUE  - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
  96   #   FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
  97   # @Prompt Enable FF-A support.
  98   gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
  99
 100 [PcdsFixedAtBuild.common]
 101   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
 102
 103   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
 104   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
 105   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
 106
 107   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
 108   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
 109
 110   #
 111   # ARM Secure Firmware PCDs
 112   #
 113   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
 114   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
 115   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
 116   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
 117
 118   #
 119   # ARM Hypervisor Firmware PCDs
 120   #
 121   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 122   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 123   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 124   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 125
 126   # Use ClusterId + CoreId to identify the PrimaryCore
 127   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 128   # The Primary Core is ClusterId[0] & CoreId[0]
 129   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 130
 131   #
 132   # SMBIOS PCDs
 133   #
 134   gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
 135   gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
 136   gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
 137   gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
 138   gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
 139   gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
 140   gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
 141   gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
 142   gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
 143   gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
 144
 145   #
 146   # ARM L2x0 PCDs
 147   #
 148   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 149
 150   #
 151   # ARM Normal (or Non Secure) Firmware PCDs
 152   #
 153   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 154   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 155
 156   #
 157   # Value to add to a host address to obtain a device address, using
 158   # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
 159   # means we can rely on truncation on overflow to specify negative
 160   # offsets.
 161   #
 162   gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
 163
 164 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
 165   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
 166   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
 167
 168 [PcdsFixedAtBuild.ARM]
 169   #
 170   # ARM Security Extension
 171   #
 172
 173   # Secure Configuration Register
 174   # - BIT0 : NS - Non Secure bit
 175   # - BIT1 : IRQ Handler
 176   # - BIT2 : FIQ Handler
 177   # - BIT3 : EA - External Abort
 178   # - BIT4 : FW - F bit writable
 179   # - BIT5 : AW - A bit writable
 180   # - BIT6 : nET - Not Early Termination
 181   # - BIT7 : SCD - Secure Monitor Call Disable
 182   # - BIT8 : HCE - Hyp Call enable
 183   # - BIT9 : SIF - Secure Instruction Fetch
 184   # 0x31 = NS | EA | FW
 185   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 186
 187   # By default we do not do a transition to non-secure mode
 188   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 189
 190   # Non Secure Access Control Register
 191   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 192   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 193   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 194   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 195   # 0xC00 = cp10 | cp11
 196   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 197
 198 [PcdsFixedAtBuild.AARCH64]
 199   #
 200   # AArch64 Security Extension
 201   #
 202
 203   # Secure Configuration Register
 204   # - BIT0 : NS - Non Secure bit
 205   # - BIT1 : IRQ Handler
 206   # - BIT2 : FIQ Handler
 207   # - BIT3 : EA - External Abort
 208   # - BIT4 : FW - F bit writable
 209   # - BIT5 : AW - A bit writable
 210   # - BIT6 : nET - Not Early Termination
 211   # - BIT7 : SCD - Secure Monitor Call Disable
 212   # - BIT8 : HCE - Hyp Call enable
 213   # - BIT9 : SIF - Secure Instruction Fetch
 214   # - BIT10: RW -  Register width control for lower exception levels
 215   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 216   # - BIT12: TWI - Trap WFI
 217   # - BIT13: TWE - Trap WFE
 218   # 0x501 = NS | HCE | RW
 219   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 220
 221   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 222   #        Mode Description              Bits
 223   # NS EL2 SP2 all interrupts disabled =  0x3c9
 224   # NS EL1 SP1 all interrupts disabled =  0x3c5
 225   # Other modes include using SP0 or switching to Aarch32, but these are
 226   # not currently supported.
 227   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 228
 229
 230 #
 231 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
 232 # redefined when using UEFI in a context of virtual machine.
 233 #
 234 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 235
 236   # System Memory (DRAM): These PCDs define the region of in-built system memory
 237   # Some platforms can get DRAM extensions, these additional regions may be
 238   # declared to UEFI using separate resource descriptor HOBs
 239   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 240   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 241
 242   gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
 243   gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
 244
 245   gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
 246   gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
 247
 248 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 249   #
 250   # ARM Architectural Timer
 251   #
 252   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 253
 254   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 255   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 256   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 257   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 258   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
 259
 260   #
 261   # ARM Generic Watchdog
 262   #
 263
 264   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
 265   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
 266   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 267
 268   #
 269   # ARM Generic Interrupt Controller
 270   #
 271   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
 272   # Base address for the GIC Redistributor region that contains the boot CPU
 273   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
 274   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
 275   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
 276
 277   #
 278   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 279   # Note that "IO" is just another MMIO range that simulates IO space; there
 280   # are no special instructions to access it.
 281   #
 282   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 283   # specific to their containing address spaces. In order to get the physical
 284   # address for the CPU, for a given access, the respective translation value
 285   # has to be added.
 286   #
 287   # The translations always have to be initialized like this, using UINT64:
 288   #
 289   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 290   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 291   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 292   #
 293   #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;
 294   #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 295   #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 296   #
 297   # because (a) the target address space (ie. the cpu-physical space) is
 298   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 299   # arithmetic.
 300   #
 301   # Accordingly, the translation itself needs to be implemented as:
 302   #
 303   #   UINT64 UntranslatedIoAddress;     // input parameter
 304   #   UINT32 UntranslatedMmio32Address; // input parameter
 305   #   UINT64 UntranslatedMmio64Address; // input parameter
 306   #
 307   #   UINT64 TranslatedIoAddress;       // output parameter
 308   #   UINT64 TranslatedMmio32Address;   // output parameter
 309   #   UINT64 TranslatedMmio64Address;   // output parameter
 310   #
 311   #   TranslatedIoAddress     = UntranslatedIoAddress +
 312   #                             PcdPciIoTranslation;
 313   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 314   #                             PcdPciMmio32Translation;
 315   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 316   #                             PcdPciMmio64Translation;
 317   #
 318   #  The modular arithmetic performed in UINT64 ensures that the translation
 319   #  works correctly regardless of the relation between IoCpuBase and
 320   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 321   #  PcdPciMmio64Base.
 322   #
 323   gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
 324   gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
 325   gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
 326   gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
 327   gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
 328   gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
 329   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
 330   gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
 331   gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
 332
 333   #
 334   # Inclusive range of allowed PCI buses.
 335   #
 336   gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
 337   gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A