ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   6 #
   7 #    This program and the accompanying materials
   8 #    are licensed and made available under the terms and conditions of the BSD License
   9 #    which accompanies this distribution. The full text of the license may be found at
  10 #    http://opensource.org/licenses/bsd-license.php
  11 #
  12 #    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 #    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14 #
  15 #**/
  16
  17 [Defines]
  18   DEC_SPECIFICATION              = 0x00010005
  19   PACKAGE_NAME                   = ArmPkg
  20   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  21   PACKAGE_VERSION                = 0.1
  22
  23 ################################################################################
  24 #
  25 # Include Section - list of Include Paths that are provided by this package.
  26 #                   Comments are used for Keywords and Module Types.
  27 #
  28 # Supported Module Types:
  29 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  30 #
  31 ################################################################################
  32 [Includes.common]
  33   Include                        # Root include for the package
  34
  35 [LibraryClasses.common]
  36   ArmLib|Include/Library/ArmLib.h
  37   SemihostLib|Include/Library/Semihosting.h
  38   UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h
  39   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  40   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  41
  42 [Guids.common]
  43   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  44
  45   ## ARM MPCore table
  46   # Include/Guid/ArmMpCoreInfo.h
  47   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
  48
  49 [Ppis]
  50   ## Include/Ppi/ArmMpCoreInfo.h
  51   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
  52
  53 [Protocols.common]
  54   gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }
  55
  56 [PcdsFeatureFlag.common]
  57   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
  58
  59   # On ARM Architecture with the Security Extension, the address for the
  60   # Vector Table can be mapped anywhere in the memory map. It means we can
  61   # point the Exception Vector Table to its location in CpuDxe.
  62   # By default we copy the Vector Table at  PcdGet32(PcdCpuVectorBaseAddress)
  63   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
  64   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
  65   # it has been configured by the CPU DXE
  66   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
  67
  68   # Define if the spin-table mechanism is used by the secondary cores when booting
  69   # Linux (instead of PSCI)
  70   gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
  71
  72 [PcdsFixedAtBuild.common]
  73   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
  74
  75   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
  76   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
  77   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
  78
  79   gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002
  80   gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003
  81   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004
  82   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
  83
  84   #
  85   # ARM Generic Interrupt Controller
  86   #
  87   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
  88   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
  89   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
  90
  91   #
  92   # ARM Secure Firmware PCDs
  93   #
  94   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015
  95   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
  96   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F
  97   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
  98
  99   #
 100   # ARM Normal (or Non Secure) Firmware PCDs
 101   #
 102   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B
 103   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 104   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D
 105   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 106
 107   #
 108   # ARM Hypervisor Firmware PCDs
 109   #
 110   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 111   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 112   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 113   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 114
 115   # System Memory (DRAM): These PCDs define the region of in-built system memory
 116   # Some platforms can get DRAM extensions, these additional regions will be declared
 117   # to UEFI by ArmPlatformLib
 118   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 119   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 120
 121   # Use ClusterId + CoreId to identify the PrimaryCore
 122   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 123   # The Primary Core is ClusterId[0] & CoreId[0]
 124   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 125
 126   #
 127   # ARM L2x0 PCDs
 128   #
 129   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 130
 131   #
 132   # BdsLib
 133   #
 134   gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E
 135   # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory
 136   gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F
 137   # Maximum file size for TFTP servers that do not support 'tsize' extension
 138   gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000
 139
 140
 141 [PcdsFixedAtBuild.ARM]
 142   #
 143   # ARM Security Extension
 144   #
 145
 146   # Secure Configuration Register
 147   # - BIT0 : NS - Non Secure bit
 148   # - BIT1 : IRQ Handler
 149   # - BIT2 : FIQ Handler
 150   # - BIT3 : EA - External Abort
 151   # - BIT4 : FW - F bit writable
 152   # - BIT5 : AW - A bit writable
 153   # - BIT6 : nET - Not Early Termination
 154   # - BIT7 : SCD - Secure Monitor Call Disable
 155   # - BIT8 : HCE - Hyp Call enable
 156   # - BIT9 : SIF - Secure Instruction Fetch
 157   # 0x31 = NS | EA | FW
 158   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 159
 160   # By default we do not do a transition to non-secure mode
 161   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 162
 163   # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
 164   gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
 165
 166   # If the fixed FDT address is not available, then it should be loaded below the kernel.
 167   # The recommendation from the Linux kernel is to have the FDT below 16KB.
 168   # (see the kernel doc: Documentation/arm/Booting)
 169   gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
 170   # The FDT blob must be loaded at a 64bit aligned address.
 171   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
 172
 173   # Non Secure Access Control Register
 174   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 175   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 176   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 177   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 178   # 0xC00 = cp10 | cp11
 179   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 180
 181 [PcdsFixedAtBuild.AARCH64]
 182   #
 183   # AArch64 Security Extension
 184   #
 185
 186   # Secure Configuration Register
 187   # - BIT0 : NS - Non Secure bit
 188   # - BIT1 : IRQ Handler
 189   # - BIT2 : FIQ Handler
 190   # - BIT3 : EA - External Abort
 191   # - BIT4 : FW - F bit writable
 192   # - BIT5 : AW - A bit writable
 193   # - BIT6 : nET - Not Early Termination
 194   # - BIT7 : SCD - Secure Monitor Call Disable
 195   # - BIT8 : HCE - Hyp Call enable
 196   # - BIT9 : SIF - Secure Instruction Fetch
 197   # - BIT10: RW -  Register width control for lower exception levels
 198   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 199   # - BIT12: TWI - Trap WFI
 200   # - BIT13: TWE - Trap WFE
 201   # 0x501 = NS | HCE | RW
 202   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 203
 204   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 205   #        Mode Description              Bits
 206   # NS EL2 SP2 all interrupts disabled =  0x3c9
 207   # NS EL1 SP1 all interrupts disabled =  0x3c5
 208   # Other modes include using SP0 or switching to Aarch32, but these are
 209   # not currently supported.
 210   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 211   # If the fixed FDT address is not available, then it should be loaded above the kernel.
 212   # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
 213   # (see the kernel doc: Documentation/arm64/booting.txt)
 214   gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
 215   # The FDT blob must be loaded at a 2MB aligned address.
 216   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
 217
 218
 219 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 220   #
 221   # ARM Architectural Timer
 222   #
 223   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 224
 225   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 226   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 227   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 228   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 229   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041