ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c

   1 /** @file
   2
   3   Copyright (c) 2011, ARM Limited. All rights reserved.
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/ArmCpuLib.h>
  18 #include <Library/ArmGicLib.h>
  19 #include <Library/IoLib.h>
  20 #include <Library/PcdLib.h>
  21
  22 VOID
  23 ArmCpuSynchronizeSignal (
  24   IN ARM_CPU_SYNCHRONIZE_EVENT   Event
  25   )
  26 {
  27   if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {
  28     // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be
  29     // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot
  30     // Mem as been initialized
  31   } else {
  32     // Send SGI to all Secondary core to wake them up from WFI state.
  33     ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
  34   }
  35 }
  36
  37 VOID
  38 CArmCpuSynchronizeWait (
  39   IN ARM_CPU_SYNCHRONIZE_EVENT   Event
  40   )
  41 {
  42   // Waiting for the SGI from the primary core
  43   ArmCallWFI ();
  44
  45   // Acknowledge the interrupt and send End of Interrupt signal.
  46   ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
  47 }
  48
  49 #if 0
  50 VOID
  51 ArmEnableScu (
  52   VOID
  53   )
  54 {
  55   INTN          ScuBase;
  56
  57   ScuBase = ArmGetScuBaseAddress();
  58
  59   // Invalidate all: write -1 to SCU Invalidate All register
  60   MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
  61   // Enable SCU
  62   MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
  63 }
  64 #endif
  65
  66 VOID
  67 ArmCpuSetup (
  68   IN  UINTN         MpId
  69   )
  70 {
  71   /*AMP mode and SMP mode
  72
  73    By default, the processor is in AMP mode (bit 5 reset to 0). To prevent coherent data corruption the sequence to turn on MP11 CPUs in SMP mode is:
  74
  75    1.Write the SCU register to change CPU mode.
  76    2.Disable interrupts.
  77    3.Clean and invalidate all the D-cache.
  78    4.Write SMP/nAMP bit as 1.
  79    5.Enable interrupts.
  80
  81   Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/BIHHFGEC.html
  82   */
  83
  84   // If MPCore then Enable the SCU
  85   if (ArmIsMpCore()) {
  86     //ArmEnableScu ();
  87   }
  88 }
  89
  90
  91 VOID
  92 ArmCpuSetupSmpNonSecure (
  93   IN  UINTN         MpId
  94   )
  95 {
  96 #if 0
  97   INTN          ScuBase;
  98
  99   ArmSetAuxCrBit (A9_FEATURE_SMP);
 100
 101   // Make the SCU accessible in Non Secure world
 102   if (IS_PRIMARY_CORE(MpId)) {
 103     ScuBase = ArmGetScuBaseAddress();
 104
 105     // Allow NS access to SCU register
 106     MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
 107     // Allow NS access to Private Peripherals
 108     MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
 109   }
 110 #endif
 111 }
 112