ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c

   1 /** @file
   2
   3   Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/ArmCpuLib.h>
  18 #include <Library/ArmGenericTimerCounterLib.h>
  19 #include <Library/DebugLib.h>
  20 #include <Library/PcdLib.h>
  21
  22 #include <Chipset/ArmCortexA15.h>
  23
  24 VOID
  25 ArmCpuSetup (
  26   IN  UINTN         MpId
  27   )
  28 {
  29   // Check if Architectural Timer frequency is valid number (should not be 0)
  30   ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
  31   ASSERT(ArmIsArchTimerImplemented () != 0);
  32
  33   // Enable SWP instructions
  34   ArmEnableSWPInstruction ();
  35
  36   // Enable program flow prediction, if supported.
  37   ArmEnableBranchPrediction ();
  38
  39   // Note: System Counter frequency can only be set in Secure privileged mode,
  40   // if security extensions are implemented.
  41   ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
  42
  43   if (ArmIsMpCore()) {
  44     // Turn on SMP coherency
  45     ArmSetAuxCrBit (A15_FEATURE_SMP);
  46   }
  47
  48 }
  49
  50
  51 VOID
  52 ArmCpuSetupSmpNonSecure (
  53   IN  UINTN         MpId
  54   )
  55 {
  56   /*// Make the SCU accessible in Non Secure world
  57   if (ArmPlatformIsPrimaryCore (MpId)) {
  58     ScuBase = ArmGetScuBaseAddress();
  59
  60     // Allow NS access to SCU register
  61     MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
  62     // Allow NS access to Private Peripherals
  63     MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
  64   }*/
  65 }