ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c

   1 /** @file
   2
   3   Copyright (c) 2011-2014, ARM Limited. All rights reserved.
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/ArmCpuLib.h>
  18 #include <Library/ArmGenericTimerCounterLib.h>
  19 #include <Library/DebugLib.h>
  20 #include <Library/PcdLib.h>
  21
  22 #include <Chipset/ArmCortexA5x.h>
  23
  24 VOID
  25 ArmCpuSetup (
  26   IN  UINTN         MpId
  27   )
  28 {
  29   // Check if Architectural Timer frequency is valid number (should not be 0)
  30   ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
  31   ASSERT (ArmIsArchTimerImplemented () != 0);
  32
  33   // Note: System Counter frequency can only be set in Secure privileged mode,
  34   // if security extensions are implemented.
  35   ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
  36
  37   if (ArmIsMpCore ()) {
  38     // Turn on SMP coherency
  39     ArmSetCpuExCrBit (A5X_FEATURE_SMP);
  40   }
  41
  42   //
  43   // If CPU is CortexA57 r0p0 apply Errata workarounds
  44   //
  45   if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
  46                          ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
  47
  48     // Errata 806969: DisableLoadStoreWB (1ULL << 49)
  49     // Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate  (1ULL << 44)
  50     // Errata 814670: disable DMB nullification (1ULL << 58)
  51     ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );
  52   }
  53 }
  54
  55 VOID
  56 ArmCpuSetupSmpNonSecure (
  57   IN  UINTN         MpId
  58   )
  59 {
  60 }
  61
  62 VOID
  63 EFIAPI
  64 ArmSetCpuExCrBit (
  65   IN  UINT64    Bits
  66   )
  67 {
  68   UINT64 Value;
  69   Value =  ArmReadCpuExCr ();
  70   Value |= Bits;
  71   ArmWriteCpuExCr (Value);
  72 }
  73
  74 VOID
  75 EFIAPI
  76 ArmUnsetCpuExCrBit (
  77   IN  UINT64    Bits
  78   )
  79 {
  80   UINT64 Value;
  81   Value = ArmReadCpuExCr ();
  82   Value &= ~Bits;
  83   ArmWriteCpuExCr (Value);
  84 }