ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S

   1 //
   2 //  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Library/ArmCpuLib.h>
  16 #include <Chipset/ArmCortexA9.h>
  17
  18 .text
  19 .align 3
  20
  21 GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
  22 GCC_ASM_EXPORT(ArmGetScuBaseAddress)
  23 GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
  24
  25 // VOID
  26 // ArmCpuSynchronizeWait (
  27 //   IN ARM_CPU_SYNCHRONIZE_EVENT   Event
  28 //   );
  29 ASM_PFX(ArmCpuSynchronizeWait):
  30   cmp   r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
  31   // The SCU enabled is the event to tell us the Init Boot Memory is initialized
  32   beq   ASM_PFX(ArmWaitScuEnabled)
  33   // Case when the stack has been set up
  34   push  {r1,lr}
  35   LoadConstantToReg (ASM_PFX(CArmCpuSynchronizeWait), r1)
  36   blx   r1
  37   pop   {r1,lr}
  38   bx    lr
  39
  40 // IN None
  41 // OUT r0 = SCU Base Address
  42 ASM_PFX(ArmGetScuBaseAddress):
  43   // Read Configuration Base Address Register. ArmCBar cannot be called to get
  44   // the Configuration BAR as a stack is not necessary setup. The SCU is at the
  45   // offset 0x0000 from the Private Memory Region.
  46   mrc   p15, 4, r0, c15, c0, 0
  47   bx  lr
  48
  49 ASM_PFX(ArmWaitScuEnabled):
  50   // Read Configuration Base Address Register. ArmCBar cannot be called to get
  51   // the Configuration BAR as a stack is not necessary setup. The SCU is at the
  52   // offset 0x0000 from the Private Memory Region.
  53   mrc   p15, 4, r0, c15, c0, 0
  54   add   r0, r0, #A9_SCU_CONTROL_OFFSET
  55   ldr   r0, [r0]
  56   cmp   r0, #1
  57   bne   ASM_PFX(ArmWaitScuEnabled)
  58   bx    lr