ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include "ArmGicDxe.h"
  16 #include "GicV3/ArmGicV3Lib.h"
  17
  18 #define ARM_GIC_DEFAULT_PRIORITY  0x80
  19
  20 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
  21
  22 STATIC UINTN mGicDistributorBase;
  23
  24 /**
  25   Enable interrupt source Source.
  26
  27   @param This     Instance pointer for this protocol
  28   @param Source   Hardware source of the interrupt
  29
  30   @retval EFI_SUCCESS       Source interrupt enabled.
  31   @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
  32
  33 **/
  34 EFI_STATUS
  35 EFIAPI
  36 GicV3EnableInterruptSource (
  37   IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
  38   IN HARDWARE_INTERRUPT_SOURCE          Source
  39   )
  40 {
  41   if (Source > mGicNumInterrupts) {
  42     ASSERT(FALSE);
  43     return EFI_UNSUPPORTED;
  44   }
  45
  46   ArmGicEnableInterrupt (mGicDistributorBase, Source);
  47
  48   return EFI_SUCCESS;
  49 }
  50
  51 /**
  52   Disable interrupt source Source.
  53
  54   @param This     Instance pointer for this protocol
  55   @param Source   Hardware source of the interrupt
  56
  57   @retval EFI_SUCCESS       Source interrupt disabled.
  58   @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
  59
  60 **/
  61 EFI_STATUS
  62 EFIAPI
  63 GicV3DisableInterruptSource (
  64   IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
  65   IN HARDWARE_INTERRUPT_SOURCE          Source
  66   )
  67 {
  68   if (Source > mGicNumInterrupts) {
  69     ASSERT(FALSE);
  70     return EFI_UNSUPPORTED;
  71   }
  72
  73   ArmGicDisableInterrupt (mGicDistributorBase, Source);
  74
  75   return EFI_SUCCESS;
  76 }
  77
  78 /**
  79   Return current state of interrupt source Source.
  80
  81   @param This     Instance pointer for this protocol
  82   @param Source   Hardware source of the interrupt
  83   @param InterruptState  TRUE: source enabled, FALSE: source disabled.
  84
  85   @retval EFI_SUCCESS       InterruptState is valid
  86   @retval EFI_DEVICE_ERROR  InterruptState is not valid
  87
  88 **/
  89 EFI_STATUS
  90 EFIAPI
  91 GicV3GetInterruptSourceState (
  92   IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
  93   IN HARDWARE_INTERRUPT_SOURCE          Source,
  94   IN BOOLEAN                            *InterruptState
  95   )
  96 {
  97   if (Source > mGicNumInterrupts) {
  98     ASSERT(FALSE);
  99     return EFI_UNSUPPORTED;
 100   }
 101
 102   *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, Source);
 103
 104   return EFI_SUCCESS;
 105 }
 106
 107 /**
 108   Signal to the hardware that the End Of Interrupt state
 109   has been reached.
 110
 111   @param This     Instance pointer for this protocol
 112   @param Source   Hardware source of the interrupt
 113
 114   @retval EFI_SUCCESS       Source interrupt EOI'ed.
 115   @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
 116
 117 **/
 118 EFI_STATUS
 119 EFIAPI
 120 GicV3EndOfInterrupt (
 121   IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
 122   IN HARDWARE_INTERRUPT_SOURCE          Source
 123   )
 124 {
 125   if (Source > mGicNumInterrupts) {
 126     ASSERT(FALSE);
 127     return EFI_UNSUPPORTED;
 128   }
 129
 130   ArmGicV3EndOfInterrupt (Source);
 131   return EFI_SUCCESS;
 132 }
 133
 134 /**
 135   EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
 136
 137   @param  InterruptType    Defines the type of interrupt or exception that
 138                            occurred on the processor.This parameter is processor architecture specific.
 139   @param  SystemContext    A pointer to the processor context when
 140                            the interrupt occurred on the processor.
 141
 142   @return None
 143
 144 **/
 145 VOID
 146 EFIAPI
 147 GicV3IrqInterruptHandler (
 148   IN EFI_EXCEPTION_TYPE           InterruptType,
 149   IN EFI_SYSTEM_CONTEXT           SystemContext
 150   )
 151 {
 152   UINT32                      GicInterrupt;
 153   HARDWARE_INTERRUPT_HANDLER  InterruptHandler;
 154
 155   GicInterrupt = ArmGicV3AcknowledgeInterrupt ();
 156
 157   // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the
 158   // number of interrupt (ie: Spurious interrupt).
 159   if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
 160     // The special interrupt do not need to be acknowledge
 161     return;
 162   }
 163
 164   InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
 165   if (InterruptHandler != NULL) {
 166     // Call the registered interrupt handler.
 167     InterruptHandler (GicInterrupt, SystemContext);
 168   } else {
 169     DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
 170   }
 171
 172   GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt);
 173 }
 174
 175 //
 176 // The protocol instance produced by this driver
 177 //
 178 EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
 179   RegisterInterruptSource,
 180   GicV3EnableInterruptSource,
 181   GicV3DisableInterruptSource,
 182   GicV3GetInterruptSourceState,
 183   GicV3EndOfInterrupt
 184 };
 185
 186 /**
 187   Shutdown our hardware
 188
 189   DXE Core will disable interrupts and turn off the timer and disable interrupts
 190   after all the event handlers have run.
 191
 192   @param[in]  Event   The Event that is being processed
 193   @param[in]  Context Event Context
 194 **/
 195 VOID
 196 EFIAPI
 197 GicV3ExitBootServicesEvent (
 198   IN EFI_EVENT  Event,
 199   IN VOID       *Context
 200   )
 201 {
 202   UINTN    Index;
 203
 204   // Acknowledge all pending interrupts
 205   for (Index = 0; Index < mGicNumInterrupts; Index++) {
 206     GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
 207   }
 208
 209   for (Index = 0; Index < mGicNumInterrupts; Index++) {
 210     GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, Index);
 211   }
 212
 213   // Disable Gic Interface
 214   ArmGicV3DisableInterruptInterface ();
 215
 216   // Disable Gic Distributor
 217   ArmGicDisableDistributor (mGicDistributorBase);
 218 }
 219
 220 /**
 221   Initialize the state information for the CPU Architectural Protocol
 222
 223   @param  ImageHandle   of the loaded driver
 224   @param  SystemTable   Pointer to the System Table
 225
 226   @retval EFI_SUCCESS           Protocol registered
 227   @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure
 228   @retval EFI_DEVICE_ERROR      Hardware problems
 229
 230 **/
 231 EFI_STATUS
 232 GicV3DxeInitialize (
 233   IN EFI_HANDLE         ImageHandle,
 234   IN EFI_SYSTEM_TABLE   *SystemTable
 235   )
 236 {
 237   EFI_STATUS              Status;
 238   UINTN                   Index;
 239   UINT32                  RegOffset;
 240   UINTN                   RegShift;
 241   UINT32                  CpuTarget;
 242
 243   // Make sure the Interrupt Controller Protocol is not already installed in the system.
 244   ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
 245
 246   mGicDistributorBase = PcdGet32 (PcdGicDistributorBase);
 247   mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
 248
 249   for (Index = 0; Index < mGicNumInterrupts; Index++) {
 250     GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
 251
 252     // Set Priority
 253     RegOffset = Index / 4;
 254     RegShift = (Index % 4) * 8;
 255     MmioAndThenOr32 (
 256       mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
 257       ~(0xff << RegShift),
 258       ARM_GIC_DEFAULT_PRIORITY << RegShift
 259       );
 260   }
 261
 262   //
 263   // Targets the interrupts to the Primary Cpu
 264   //
 265
 266   // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
 267   // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
 268   // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
 269   // More Info in the GIC Specification about "Interrupt Processor Targets Registers"
 270   //
 271   // Read the first Interrupt Processor Targets Register (that corresponds to the 4
 272   // first SGIs)
 273   CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
 274
 275   // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
 276   // is 0 when we run on a uniprocessor platform.
 277   if (CpuTarget != 0) {
 278     // The 8 first Interrupt Processor Targets Registers are read-only
 279     for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
 280       MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
 281     }
 282   }
 283
 284   // Set binary point reg to 0x7 (no preemption)
 285   ArmGicV3SetBinaryPointer (0x7);
 286
 287   // Set priority mask reg to 0xff to allow all priorities through
 288   ArmGicV3SetPriorityMask (0xff);
 289
 290   // Enable gic cpu interface
 291   ArmGicV3EnableInterruptInterface ();
 292
 293   // Enable gic distributor
 294   ArmGicEnableDistributor (mGicDistributorBase);
 295
 296   Status = InstallAndRegisterInterruptService (
 297           &gHardwareInterruptV3Protocol, GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent);
 298
 299   return Status;
 300 }