2 Produces the CPU I/O 2 Protocol.
4 Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
13 #include <Protocol/CpuIo2.h>
15 #include <Library/BaseLib.h>
16 #include <Library/DebugLib.h>
17 #include <Library/IoLib.h>
18 #include <Library/PcdLib.h>
19 #include <Library/UefiBootServicesTableLib.h>
21 #define MAX_IO_PORT_ADDRESS 0xFFFF
24 // Handle for the CPU I/O 2 Protocol
26 STATIC EFI_HANDLE mHandle
= NULL
;
29 // Lookup table for increment values based on transfer widths
31 STATIC CONST UINT8 mInStride
[] = {
32 1, // EfiCpuIoWidthUint8
33 2, // EfiCpuIoWidthUint16
34 4, // EfiCpuIoWidthUint32
35 8, // EfiCpuIoWidthUint64
36 0, // EfiCpuIoWidthFifoUint8
37 0, // EfiCpuIoWidthFifoUint16
38 0, // EfiCpuIoWidthFifoUint32
39 0, // EfiCpuIoWidthFifoUint64
40 1, // EfiCpuIoWidthFillUint8
41 2, // EfiCpuIoWidthFillUint16
42 4, // EfiCpuIoWidthFillUint32
43 8 // EfiCpuIoWidthFillUint64
47 // Lookup table for increment values based on transfer widths
49 STATIC CONST UINT8 mOutStride
[] = {
50 1, // EfiCpuIoWidthUint8
51 2, // EfiCpuIoWidthUint16
52 4, // EfiCpuIoWidthUint32
53 8, // EfiCpuIoWidthUint64
54 1, // EfiCpuIoWidthFifoUint8
55 2, // EfiCpuIoWidthFifoUint16
56 4, // EfiCpuIoWidthFifoUint32
57 8, // EfiCpuIoWidthFifoUint64
58 0, // EfiCpuIoWidthFillUint8
59 0, // EfiCpuIoWidthFillUint16
60 0, // EfiCpuIoWidthFillUint32
61 0 // EfiCpuIoWidthFillUint64
65 Check parameters to a CPU I/O 2 Protocol service request.
67 The I/O operations are carried out exactly as requested. The caller is responsible
68 for satisfying any alignment and I/O width restrictions that a PI System on a
69 platform might require. For example on some platforms, width requests of
70 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
71 be handled by the driver.
73 @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
74 @param[in] Width Signifies the width of the I/O or Memory operation.
75 @param[in] Address The base address of the I/O operation.
76 @param[in] Count The number of I/O operations to perform. The number of
77 bytes moved is Width size * Count, starting at Address.
78 @param[in] Buffer For read operations, the destination buffer to store the results.
79 For write operations, the source buffer from which to write data.
81 @retval EFI_SUCCESS The parameters for this request pass the checks.
82 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
83 @retval EFI_INVALID_PARAMETER Buffer is NULL.
84 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
85 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
86 and Count is not valid for this PI system.
92 IN BOOLEAN MmioOperation
,
93 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
103 // Check to see if Buffer is NULL
105 if (Buffer
== NULL
) {
106 return EFI_INVALID_PARAMETER
;
110 // Check to see if Width is in the valid range
112 if ((UINT32
)Width
>= EfiCpuIoWidthMaximum
) {
113 return EFI_INVALID_PARAMETER
;
117 // For FIFO type, the target address won't increase during the access,
118 // so treat Count as 1
120 if (Width
>= EfiCpuIoWidthFifoUint8
&& Width
<= EfiCpuIoWidthFifoUint64
) {
125 // Check to see if Width is in the valid range for I/O Port operations
127 Width
= (EFI_CPU_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
128 if (!MmioOperation
&& (Width
== EfiCpuIoWidthUint64
)) {
129 return EFI_INVALID_PARAMETER
;
133 // Check to see if Address is aligned
135 if ((Address
& (UINT64
)(mInStride
[Width
] - 1)) != 0) {
136 return EFI_UNSUPPORTED
;
140 // Check to see if any address associated with this transfer exceeds the maximum
141 // allowed address. The maximum address implied by the parameters passed in is
142 // Address + Size * Count. If the following condition is met, then the transfer
145 // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
147 // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
148 // can also be the maximum integer value supported by the CPU, this range
149 // check must be adjusted to avoid all oveflow conditions.
151 // The following form of the range check is equivalent but assumes that
152 // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
154 Limit
= (MmioOperation
? MAX_ADDRESS
: MAX_IO_PORT_ADDRESS
);
156 if (Address
> Limit
) {
157 return EFI_UNSUPPORTED
;
160 MaxCount
= RShiftU64 (Limit
, Width
);
161 if (MaxCount
< (Count
- 1)) {
162 return EFI_UNSUPPORTED
;
164 if (Address
> LShiftU64 (MaxCount
- Count
+ 1, Width
)) {
165 return EFI_UNSUPPORTED
;
170 // Check to see if Buffer is aligned
172 if (((UINTN
)Buffer
& ((MIN (sizeof (UINTN
), mInStride
[Width
]) - 1))) != 0) {
173 return EFI_UNSUPPORTED
;
180 Reads memory-mapped registers.
182 The I/O operations are carried out exactly as requested. The caller is responsible
183 for satisfying any alignment and I/O width restrictions that a PI System on a
184 platform might require. For example on some platforms, width requests of
185 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
186 be handled by the driver.
188 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
189 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
190 each of the Count operations that is performed.
192 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
193 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
194 incremented for each of the Count operations that is performed. The read or
195 write operation is performed Count times on the same Address.
197 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
198 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
199 incremented for each of the Count operations that is performed. The read or
200 write operation is performed Count times from the first element of Buffer.
202 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
203 @param[in] Width Signifies the width of the I/O or Memory operation.
204 @param[in] Address The base address of the I/O operation.
205 @param[in] Count The number of I/O operations to perform. The number of
206 bytes moved is Width size * Count, starting at Address.
207 @param[out] Buffer For read operations, the destination buffer to store the results.
208 For write operations, the source buffer from which to write data.
210 @retval EFI_SUCCESS The data was read from or written to the PI system.
211 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
212 @retval EFI_INVALID_PARAMETER Buffer is NULL.
213 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
214 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
215 and Count is not valid for this PI system.
221 CpuMemoryServiceRead (
222 IN EFI_CPU_IO2_PROTOCOL
*This
,
223 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
232 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
235 Status
= CpuIoCheckParameter (TRUE
, Width
, Address
, Count
, Buffer
);
236 if (EFI_ERROR (Status
)) {
241 // Select loop based on the width of the transfer
243 InStride
= mInStride
[Width
];
244 OutStride
= mOutStride
[Width
];
245 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
246 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
247 if (OperationWidth
== EfiCpuIoWidthUint8
) {
248 *Uint8Buffer
= MmioRead8 ((UINTN
)Address
);
249 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
250 *((UINT16
*)Uint8Buffer
) = MmioRead16 ((UINTN
)Address
);
251 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
252 *((UINT32
*)Uint8Buffer
) = MmioRead32 ((UINTN
)Address
);
253 } else if (OperationWidth
== EfiCpuIoWidthUint64
) {
254 *((UINT64
*)Uint8Buffer
) = MmioRead64 ((UINTN
)Address
);
261 Writes memory-mapped registers.
263 The I/O operations are carried out exactly as requested. The caller is responsible
264 for satisfying any alignment and I/O width restrictions that a PI System on a
265 platform might require. For example on some platforms, width requests of
266 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
267 be handled by the driver.
269 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
270 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
271 each of the Count operations that is performed.
273 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
274 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
275 incremented for each of the Count operations that is performed. The read or
276 write operation is performed Count times on the same Address.
278 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
279 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
280 incremented for each of the Count operations that is performed. The read or
281 write operation is performed Count times from the first element of Buffer.
283 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
284 @param[in] Width Signifies the width of the I/O or Memory operation.
285 @param[in] Address The base address of the I/O operation.
286 @param[in] Count The number of I/O operations to perform. The number of
287 bytes moved is Width size * Count, starting at Address.
288 @param[in] Buffer For read operations, the destination buffer to store the results.
289 For write operations, the source buffer from which to write data.
291 @retval EFI_SUCCESS The data was read from or written to the PI system.
292 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
293 @retval EFI_INVALID_PARAMETER Buffer is NULL.
294 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
295 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
296 and Count is not valid for this PI system.
302 CpuMemoryServiceWrite (
303 IN EFI_CPU_IO2_PROTOCOL
*This
,
304 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
313 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
316 Status
= CpuIoCheckParameter (TRUE
, Width
, Address
, Count
, Buffer
);
317 if (EFI_ERROR (Status
)) {
322 // Select loop based on the width of the transfer
324 InStride
= mInStride
[Width
];
325 OutStride
= mOutStride
[Width
];
326 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
327 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
328 if (OperationWidth
== EfiCpuIoWidthUint8
) {
329 MmioWrite8 ((UINTN
)Address
, *Uint8Buffer
);
330 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
331 MmioWrite16 ((UINTN
)Address
, *((UINT16
*)Uint8Buffer
));
332 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
333 MmioWrite32 ((UINTN
)Address
, *((UINT32
*)Uint8Buffer
));
334 } else if (OperationWidth
== EfiCpuIoWidthUint64
) {
335 MmioWrite64 ((UINTN
)Address
, *((UINT64
*)Uint8Buffer
));
344 The I/O operations are carried out exactly as requested. The caller is responsible
345 for satisfying any alignment and I/O width restrictions that a PI System on a
346 platform might require. For example on some platforms, width requests of
347 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
348 be handled by the driver.
350 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
351 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
352 each of the Count operations that is performed.
354 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
355 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
356 incremented for each of the Count operations that is performed. The read or
357 write operation is performed Count times on the same Address.
359 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
360 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
361 incremented for each of the Count operations that is performed. The read or
362 write operation is performed Count times from the first element of Buffer.
364 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
365 @param[in] Width Signifies the width of the I/O or Memory operation.
366 @param[in] Address The base address of the I/O operation.
367 @param[in] Count The number of I/O operations to perform. The number of
368 bytes moved is Width size * Count, starting at Address.
369 @param[out] Buffer For read operations, the destination buffer to store the results.
370 For write operations, the source buffer from which to write data.
372 @retval EFI_SUCCESS The data was read from or written to the PI system.
373 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
374 @retval EFI_INVALID_PARAMETER Buffer is NULL.
375 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
376 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
377 and Count is not valid for this PI system.
384 IN EFI_CPU_IO2_PROTOCOL
*This
,
385 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
394 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
397 Status
= CpuIoCheckParameter (FALSE
, Width
, Address
, Count
, Buffer
);
398 if (EFI_ERROR (Status
)) {
402 Address
+= PcdGet64 (PcdPciIoTranslation
);
405 // Select loop based on the width of the transfer
407 InStride
= mInStride
[Width
];
408 OutStride
= mOutStride
[Width
];
409 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
411 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
412 if (OperationWidth
== EfiCpuIoWidthUint8
) {
413 *Uint8Buffer
= MmioRead8 ((UINTN
)Address
);
414 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
415 *((UINT16
*)Uint8Buffer
) = MmioRead16 ((UINTN
)Address
);
416 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
417 *((UINT32
*)Uint8Buffer
) = MmioRead32 ((UINTN
)Address
);
427 The I/O operations are carried out exactly as requested. The caller is responsible
428 for satisfying any alignment and I/O width restrictions that a PI System on a
429 platform might require. For example on some platforms, width requests of
430 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
431 be handled by the driver.
433 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
434 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
435 each of the Count operations that is performed.
437 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
438 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
439 incremented for each of the Count operations that is performed. The read or
440 write operation is performed Count times on the same Address.
442 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
443 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
444 incremented for each of the Count operations that is performed. The read or
445 write operation is performed Count times from the first element of Buffer.
447 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
448 @param[in] Width Signifies the width of the I/O or Memory operation.
449 @param[in] Address The base address of the I/O operation.
450 @param[in] Count The number of I/O operations to perform. The number of
451 bytes moved is Width size * Count, starting at Address.
452 @param[in] Buffer For read operations, the destination buffer to store the results.
453 For write operations, the source buffer from which to write data.
455 @retval EFI_SUCCESS The data was read from or written to the PI system.
456 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
457 @retval EFI_INVALID_PARAMETER Buffer is NULL.
458 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
459 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
460 and Count is not valid for this PI system.
467 IN EFI_CPU_IO2_PROTOCOL
*This
,
468 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
477 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
481 // Make sure the parameters are valid
483 Status
= CpuIoCheckParameter (FALSE
, Width
, Address
, Count
, Buffer
);
484 if (EFI_ERROR (Status
)) {
488 Address
+= PcdGet64 (PcdPciIoTranslation
);
491 // Select loop based on the width of the transfer
493 InStride
= mInStride
[Width
];
494 OutStride
= mOutStride
[Width
];
495 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
497 for (Uint8Buffer
= (UINT8
*)Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
498 if (OperationWidth
== EfiCpuIoWidthUint8
) {
499 MmioWrite8 ((UINTN
)Address
, *Uint8Buffer
);
500 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
501 MmioWrite16 ((UINTN
)Address
, *((UINT16
*)Uint8Buffer
));
502 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
503 MmioWrite32 ((UINTN
)Address
, *((UINT32
*)Uint8Buffer
));
511 // CPU I/O 2 Protocol instance
513 STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2
= {
515 CpuMemoryServiceRead
,
516 CpuMemoryServiceWrite
526 The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
528 @param[in] ImageHandle The firmware allocated handle for the EFI image.
529 @param[in] SystemTable A pointer to the EFI System Table.
531 @retval EFI_SUCCESS The entry point is executed successfully.
532 @retval other Some error occurs when executing this entry point.
537 ArmPciCpuIo2Initialize (
538 IN EFI_HANDLE ImageHandle
,
539 IN EFI_SYSTEM_TABLE
*SystemTable
544 ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL
, &gEfiCpuIo2ProtocolGuid
);
545 Status
= gBS
->InstallMultipleProtocolInterfaces (
547 &gEfiCpuIo2ProtocolGuid
, &mCpuIo2
,
550 ASSERT_EFI_ERROR (Status
);