1 #------------------------------------------------------------------------------
3 # Use ARMv6 instruction to operate on a single stack
5 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
7 # This program and the accompanying materials
8 # are licensed and made available under the terms and conditions of the BSD License
9 # which accompanies this distribution. The full text of the license may be found at
10 # http://opensource.org/licenses/bsd-license.php
12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #------------------------------------------------------------------------------
19 This is the stack constructed by the exception handler (low address to high address)
20 # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
23 R0 0x00 # stmfd SP!,{R0-R12}
36 SP 0x34 # reserved via adding 0x20 (32) to the SP
45 LR 0x54 # SVC Link register (we need to restore it)
47 LR 0x58 # pushed by srsfd
53 .globl ASM_PFX(ExceptionHandlersStart)
54 .globl ASM_PFX(ExceptionHandlersEnd)
55 .globl ASM_PFX(CommonExceptionEntry)
56 .globl ASM_PFX(AsmCommonExceptionEntry)
57 .globl ASM_PFX(CommonCExceptionHandler)
60 #if !defined(__APPLE__)
61 .fpu neon @ makes vpush/vpop assemble
67 // This code gets copied to the ARM vector table
68 // ExceptionHandlersStart - ExceptionHandlersEnd gets copied
70 ASM_PFX(ExceptionHandlersStart):
75 ASM_PFX(UndefinedInstruction):
76 b ASM_PFX(UndefinedInstructionEntry)
78 ASM_PFX(SoftwareInterrupt):
79 b ASM_PFX(SoftwareInterruptEntry)
81 ASM_PFX(PrefetchAbort):
82 b ASM_PFX(PrefetchAbortEntry)
85 b ASM_PFX(DataAbortEntry)
87 ASM_PFX(ReservedException):
88 b ASM_PFX(ReservedExceptionEntry)
97 srsdb #0x13! @ Store return state on SVC stack
98 @ We are already in SVC mode
100 stmfd SP!,{LR} @ Store the link register for the current mode
101 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
102 stmfd SP!,{R0-R12} @ Store the register state
104 mov R0,#0 @ ExceptionType
105 ldr R1,ASM_PFX(CommonExceptionEntry)
108 ASM_PFX(UndefinedInstructionEntry):
109 sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
110 srsdb #0x13! @ Store return state on SVC stack
111 cps #0x13 @ Switch to SVC for common stack
112 stmfd SP!,{LR} @ Store the link register for the current mode
113 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
114 stmfd SP!,{R0-R12} @ Store the register state
116 mov R0,#1 @ ExceptionType
117 ldr R1,ASM_PFX(CommonExceptionEntry)
120 ASM_PFX(SoftwareInterruptEntry):
121 sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
122 srsdb #0x13! @ Store return state on SVC stack
123 @ We are already in SVC mode
124 stmfd SP!,{LR} @ Store the link register for the current mode
125 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
126 stmfd SP!,{R0-R12} @ Store the register state
128 mov R0,#2 @ ExceptionType
129 ldr R1,ASM_PFX(CommonExceptionEntry)
132 ASM_PFX(PrefetchAbortEntry):
134 srsdb #0x13! @ Store return state on SVC stack
135 cps #0x13 @ Switch to SVC for common stack
136 stmfd SP!,{LR} @ Store the link register for the current mode
137 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
138 stmfd SP!,{R0-R12} @ Store the register state
140 mov R0,#3 @ ExceptionType
141 ldr R1,ASM_PFX(CommonExceptionEntry)
144 ASM_PFX(DataAbortEntry):
146 srsdb #0x13! @ Store return state on SVC stack
147 cps #0x13 @ Switch to SVC for common stack
148 stmfd SP!,{LR} @ Store the link register for the current mode
149 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
150 stmfd SP!,{R0-R12} @ Store the register state
153 ldr R1,ASM_PFX(CommonExceptionEntry)
156 ASM_PFX(ReservedExceptionEntry):
157 srsdb #0x13! @ Store return state on SVC stack
158 cps #0x13 @ Switch to SVC for common stack
159 stmfd SP!,{LR} @ Store the link register for the current mode
160 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
161 stmfd SP!,{R0-R12} @ Store the register state
164 ldr R1,ASM_PFX(CommonExceptionEntry)
169 srsdb #0x13! @ Store return state on SVC stack
170 cps #0x13 @ Switch to SVC for common stack
171 stmfd SP!,{LR} @ Store the link register for the current mode
172 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
173 stmfd SP!,{R0-R12} @ Store the register state
175 mov R0,#6 @ ExceptionType
176 ldr R1,ASM_PFX(CommonExceptionEntry)
181 srsdb #0x13! @ Store return state on SVC stack
182 cps #0x13 @ Switch to SVC for common stack
183 stmfd SP!,{LR} @ Store the link register for the current mode
184 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
185 stmfd SP!,{R0-R12} @ Store the register state
186 @ Since we have already switch to SVC R8_fiq - R12_fiq
187 @ never get used or saved
188 mov R0,#7 @ ExceptionType
189 ldr R1,ASM_PFX(CommonExceptionEntry)
193 // This gets patched by the C code that patches in the vector table
195 ASM_PFX(CommonExceptionEntry):
201 ASM_PFX(ExceptionHandlersEnd):
204 // This code runs from CpuDxe driver loaded address. It is patched into
205 // CommonExceptionEntry.
207 ASM_PFX(AsmCommonExceptionEntry):
208 mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
209 str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
211 mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
212 str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
214 mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
215 str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
217 mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
218 str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
220 ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
221 str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
223 add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
224 and R3, R1, #0x1f @ Check CPSR to see if User or System Mode
225 cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))
227 stmeqed R2, {lr}^ @ save unbanked lr
229 stmneed R2, {lr} @ save SVC lr
232 ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
233 @ Check to see if we have to adjust for Thumb entry
234 sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {
235 cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
238 tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
239 addne R5, R5, #2 @ PC += 2@
240 str R5,[SP,#0x58] @ Update LR value pused by srsfd
244 str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
246 sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
247 str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
249 @ R0 is ExceptionType
250 mov R1,SP @ R1 is SystemContext
252 vpush {d0-d15} @ save vstm registers in case they are used in optimizations
258 CommonCExceptionHandler (
259 IN EFI_EXCEPTION_TYPE ExceptionType, R0
260 IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
264 blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
268 ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
269 mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
271 ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
272 mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
274 ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
275 str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
277 ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
278 str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
280 add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry
281 add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
282 and R1, R1, #0x1f @ Check to see if User or System Mode
283 cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
285 ldmeqed R2, {lr}^ @ restore unbanked lr
287 ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}
289 ldmfd SP!,{R0-R12} @ Restore general purpose registers
290 @ Exception handler can not change SP
292 add SP,SP,#0x20 @ Clear out the remaining stack space
293 ldmfd SP!,{LR} @ restore the link register for this context
294 rfefd SP! @ return from exception via srsfd stack slot