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ArmPkg/ArmLib: Clean ArmV7Lib
[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / Mmu.c
1 /*++
2
3 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
4 Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14
15 --*/
16
17 #include "CpuDxe.h"
18
19 // First Level Descriptors
20 typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
21
22 // Second Level Descriptors
23 typedef UINT32 ARM_PAGE_TABLE_ENTRY;
24
25 EFI_STATUS
26 SectionToGcdAttributes (
27 IN UINT32 SectionAttributes,
28 OUT UINT64 *GcdAttributes
29 )
30 {
31 *GcdAttributes = 0;
32
33 // determine cacheability attributes
34 switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {
35 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:
36 *GcdAttributes |= EFI_MEMORY_UC;
37 break;
38 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE:
39 *GcdAttributes |= EFI_MEMORY_UC;
40 break;
41 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:
42 *GcdAttributes |= EFI_MEMORY_WT;
43 break;
44 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC:
45 *GcdAttributes |= EFI_MEMORY_WB;
46 break;
47 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE:
48 *GcdAttributes |= EFI_MEMORY_WC;
49 break;
50 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC:
51 *GcdAttributes |= EFI_MEMORY_WB;
52 break;
53 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE:
54 *GcdAttributes |= EFI_MEMORY_UC;
55 break;
56 default:
57 return EFI_UNSUPPORTED;
58 }
59
60 // determine protection attributes
61 switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
62 case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write
63 //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;
64 break;
65
66 case TT_DESCRIPTOR_SECTION_AP_RW_NO:
67 case TT_DESCRIPTOR_SECTION_AP_RW_RW:
68 // normal read/write access, do not add additional attributes
69 break;
70
71 // read only cases map to write-protect
72 case TT_DESCRIPTOR_SECTION_AP_RO_NO:
73 case TT_DESCRIPTOR_SECTION_AP_RO_RO:
74 *GcdAttributes |= EFI_MEMORY_WP;
75 break;
76
77 default:
78 return EFI_UNSUPPORTED;
79 }
80
81 // now process eXectue Never attribute
82 if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {
83 *GcdAttributes |= EFI_MEMORY_XP;
84 }
85
86 return EFI_SUCCESS;
87 }
88
89 EFI_STATUS
90 PageToGcdAttributes (
91 IN UINT32 PageAttributes,
92 OUT UINT64 *GcdAttributes
93 )
94 {
95 *GcdAttributes = 0;
96
97 // determine cacheability attributes
98 switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {
99 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:
100 *GcdAttributes |= EFI_MEMORY_UC;
101 break;
102 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE:
103 *GcdAttributes |= EFI_MEMORY_UC;
104 break;
105 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:
106 *GcdAttributes |= EFI_MEMORY_WT;
107 break;
108 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC:
109 *GcdAttributes |= EFI_MEMORY_WB;
110 break;
111 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE:
112 *GcdAttributes |= EFI_MEMORY_WC;
113 break;
114 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC:
115 *GcdAttributes |= EFI_MEMORY_WB;
116 break;
117 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE:
118 *GcdAttributes |= EFI_MEMORY_UC;
119 break;
120 default:
121 return EFI_UNSUPPORTED;
122 }
123
124 // determine protection attributes
125 switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {
126 case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write
127 //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;
128 break;
129
130 case TT_DESCRIPTOR_PAGE_AP_RW_NO:
131 case TT_DESCRIPTOR_PAGE_AP_RW_RW:
132 // normal read/write access, do not add additional attributes
133 break;
134
135 // read only cases map to write-protect
136 case TT_DESCRIPTOR_PAGE_AP_RO_NO:
137 case TT_DESCRIPTOR_PAGE_AP_RO_RO:
138 *GcdAttributes |= EFI_MEMORY_WP;
139 break;
140
141 default:
142 return EFI_UNSUPPORTED;
143 }
144
145 // now process eXectue Never attribute
146 if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) {
147 *GcdAttributes |= EFI_MEMORY_XP;
148 }
149
150 return EFI_SUCCESS;
151 }
152
153 /**
154 Searches memory descriptors covered by given memory range.
155
156 This function searches into the Gcd Memory Space for descriptors
157 (from StartIndex to EndIndex) that contains the memory range
158 specified by BaseAddress and Length.
159
160 @param MemorySpaceMap Gcd Memory Space Map as array.
161 @param NumberOfDescriptors Number of descriptors in map.
162 @param BaseAddress BaseAddress for the requested range.
163 @param Length Length for the requested range.
164 @param StartIndex Start index into the Gcd Memory Space Map.
165 @param EndIndex End index into the Gcd Memory Space Map.
166
167 @retval EFI_SUCCESS Search successfully.
168 @retval EFI_NOT_FOUND The requested descriptors does not exist.
169
170 **/
171 EFI_STATUS
172 SearchGcdMemorySpaces (
173 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
174 IN UINTN NumberOfDescriptors,
175 IN EFI_PHYSICAL_ADDRESS BaseAddress,
176 IN UINT64 Length,
177 OUT UINTN *StartIndex,
178 OUT UINTN *EndIndex
179 )
180 {
181 UINTN Index;
182
183 *StartIndex = 0;
184 *EndIndex = 0;
185 for (Index = 0; Index < NumberOfDescriptors; Index++) {
186 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
187 BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
188 *StartIndex = Index;
189 }
190 if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
191 BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
192 *EndIndex = Index;
193 return EFI_SUCCESS;
194 }
195 }
196 return EFI_NOT_FOUND;
197 }
198
199
200 /**
201 Sets the attributes for a specified range in Gcd Memory Space Map.
202
203 This function sets the attributes for a specified range in
204 Gcd Memory Space Map.
205
206 @param MemorySpaceMap Gcd Memory Space Map as array
207 @param NumberOfDescriptors Number of descriptors in map
208 @param BaseAddress BaseAddress for the range
209 @param Length Length for the range
210 @param Attributes Attributes to set
211
212 @retval EFI_SUCCESS Memory attributes set successfully
213 @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
214
215 **/
216 EFI_STATUS
217 SetGcdMemorySpaceAttributes (
218 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
219 IN UINTN NumberOfDescriptors,
220 IN EFI_PHYSICAL_ADDRESS BaseAddress,
221 IN UINT64 Length,
222 IN UINT64 Attributes
223 )
224 {
225 EFI_STATUS Status;
226 UINTN Index;
227 UINTN StartIndex;
228 UINTN EndIndex;
229 EFI_PHYSICAL_ADDRESS RegionStart;
230 UINT64 RegionLength;
231
232 //
233 // Get all memory descriptors covered by the memory range
234 //
235 Status = SearchGcdMemorySpaces (
236 MemorySpaceMap,
237 NumberOfDescriptors,
238 BaseAddress,
239 Length,
240 &StartIndex,
241 &EndIndex
242 );
243 if (EFI_ERROR (Status)) {
244 return Status;
245 }
246
247 //
248 // Go through all related descriptors and set attributes accordingly
249 //
250 for (Index = StartIndex; Index <= EndIndex; Index++) {
251 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
252 continue;
253 }
254 //
255 // Calculate the start and end address of the overlapping range
256 //
257 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
258 RegionStart = BaseAddress;
259 } else {
260 RegionStart = MemorySpaceMap[Index].BaseAddress;
261 }
262 if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
263 RegionLength = BaseAddress + Length - RegionStart;
264 } else {
265 RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
266 }
267 //
268 // Set memory attributes according to MTRR attribute and the original attribute of descriptor
269 //
270 gDS->SetMemorySpaceAttributes (
271 RegionStart,
272 RegionLength,
273 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
274 );
275 }
276
277 return EFI_SUCCESS;
278 }
279
280 EFI_STATUS
281 SyncCacheConfigPage (
282 IN UINT32 SectionIndex,
283 IN UINT32 FirstLevelDescriptor,
284 IN UINTN NumberOfDescriptors,
285 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
286 IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,
287 IN OUT UINT64 *NextRegionLength,
288 IN OUT UINT32 *NextSectionAttributes
289 )
290 {
291 EFI_STATUS Status;
292 UINT32 i;
293 volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
294 UINT32 NextPageAttributes = 0;
295 UINT32 PageAttributes = 0;
296 UINT32 BaseAddress;
297 UINT64 GcdAttributes;
298
299 // Get the Base Address from FirstLevelDescriptor;
300 BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
301
302 // Convert SectionAttributes into PageAttributes
303 NextPageAttributes =
304 TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) |
305 TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes);
306
307 // obtain page table base
308 SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
309
310 for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
311 if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {
312 // extract attributes (cacheability and permissions)
313 PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);
314
315 if (NextPageAttributes == 0) {
316 // start on a new region
317 *NextRegionLength = 0;
318 *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
319 NextPageAttributes = PageAttributes;
320 } else if (PageAttributes != NextPageAttributes) {
321 // Convert Section Attributes into GCD Attributes
322 Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);
323 ASSERT_EFI_ERROR (Status);
324
325 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
326 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
327
328 // start on a new region
329 *NextRegionLength = 0;
330 *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
331 NextPageAttributes = PageAttributes;
332 }
333 } else if (NextPageAttributes != 0) {
334 // Convert Page Attributes into GCD Attributes
335 Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);
336 ASSERT_EFI_ERROR (Status);
337
338 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
339 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
340
341 *NextRegionLength = 0;
342 *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
343 NextPageAttributes = 0;
344 }
345 *NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;
346 }
347
348 // Convert back PageAttributes into SectionAttributes
349 *NextSectionAttributes =
350 TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) |
351 TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes);
352
353 return EFI_SUCCESS;
354 }
355
356 EFI_STATUS
357 SyncCacheConfig (
358 IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
359 )
360 {
361 EFI_STATUS Status;
362 UINT32 i;
363 EFI_PHYSICAL_ADDRESS NextRegionBase;
364 UINT64 NextRegionLength;
365 UINT32 NextSectionAttributes = 0;
366 UINT32 SectionAttributes = 0;
367 UINT64 GcdAttributes;
368 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
369 UINTN NumberOfDescriptors;
370 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
371
372
373 DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));
374
375 // This code assumes MMU is enabled and filed with section translations
376 ASSERT (ArmMmuEnabled ());
377
378 //
379 // Get the memory space map from GCD
380 //
381 MemorySpaceMap = NULL;
382 Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
383 ASSERT_EFI_ERROR (Status);
384
385
386 // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
387 // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
388 // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
389 // a client) to update its copy of the attributes. This is bad architecture and should be replaced
390 // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
391
392 // obtain page table base
393 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());
394
395 // Get the first region
396 NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
397
398 // iterate through each 1MB descriptor
399 NextRegionBase = NextRegionLength = 0;
400 for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {
401 if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
402 // extract attributes (cacheability and permissions)
403 SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
404
405 if (NextSectionAttributes == 0) {
406 // start on a new region
407 NextRegionLength = 0;
408 NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
409 NextSectionAttributes = SectionAttributes;
410 } else if (SectionAttributes != NextSectionAttributes) {
411 // Convert Section Attributes into GCD Attributes
412 Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);
413 ASSERT_EFI_ERROR (Status);
414
415 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
416 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
417
418 // start on a new region
419 NextRegionLength = 0;
420 NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
421 NextSectionAttributes = SectionAttributes;
422 }
423 NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
424 } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {
425 Status = SyncCacheConfigPage (
426 i,FirstLevelTable[i],
427 NumberOfDescriptors, MemorySpaceMap,
428 &NextRegionBase,&NextRegionLength,&NextSectionAttributes);
429 ASSERT_EFI_ERROR (Status);
430 } else {
431 // We do not support yet 16MB sections
432 ASSERT ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) != TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION);
433
434 // start on a new region
435 if (NextSectionAttributes != 0) {
436 // Convert Section Attributes into GCD Attributes
437 Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);
438 ASSERT_EFI_ERROR (Status);
439
440 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
441 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
442
443 NextRegionLength = 0;
444 NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
445 NextSectionAttributes = 0;
446 }
447 NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
448 }
449 } // section entry loop
450
451 if (NextSectionAttributes != 0) {
452 // Convert Section Attributes into GCD Attributes
453 Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);
454 ASSERT_EFI_ERROR (Status);
455
456 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
457 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
458 }
459
460 return EFI_SUCCESS;
461 }
462
463
464
465 EFI_STATUS
466 UpdatePageEntries (
467 IN EFI_PHYSICAL_ADDRESS BaseAddress,
468 IN UINT64 Length,
469 IN UINT64 Attributes,
470 IN EFI_PHYSICAL_ADDRESS VirtualMask
471 )
472 {
473 EFI_STATUS Status;
474 UINT32 EntryValue;
475 UINT32 EntryMask;
476 UINT32 FirstLevelIdx;
477 UINT32 Offset;
478 UINT32 NumPageEntries;
479 UINT32 Descriptor;
480 UINT32 p;
481 UINT32 PageTableIndex;
482 UINT32 PageTableEntry;
483 UINT32 CurrentPageTableEntry;
484 VOID *Mva;
485
486 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
487 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
488
489 Status = EFI_SUCCESS;
490
491 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
492 // EntryValue: values at bit positions specified by EntryMask
493 EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK;
494 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
495 // Although the PI spec is unclear on this the GCD guarantees that only
496 // one Attribute bit is set at a time, so we can safely use a switch statement
497 switch (Attributes) {
498 case EFI_MEMORY_UC:
499 // modify cacheability attributes
500 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
501 if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
502 // map to strongly ordered
503 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
504 } else {
505 // map to normal non-cachable
506 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
507 }
508 break;
509
510 case EFI_MEMORY_WC:
511 // modify cacheability attributes
512 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
513 // map to normal non-cachable
514 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
515 break;
516
517 case EFI_MEMORY_WT:
518 // modify cacheability attributes
519 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
520 // write through with no-allocate
521 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
522 break;
523
524 case EFI_MEMORY_WB:
525 // modify cacheability attributes
526 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
527 // write back (with allocate)
528 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
529 break;
530
531 case EFI_MEMORY_WP:
532 case EFI_MEMORY_XP:
533 case EFI_MEMORY_UCE:
534 // cannot be implemented UEFI definition unclear for ARM
535 // Cause a page fault if these ranges are accessed.
536 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT;
537 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
538 break;
539
540 default:
541 return EFI_UNSUPPORTED;
542 }
543
544 // Obtain page table base
545 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
546
547 // Calculate number of 4KB page table entries to change
548 NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;
549
550 // Iterate for the number of 4KB pages to change
551 Offset = 0;
552 for(p = 0; p < NumPageEntries; p++) {
553 // Calculate index into first level translation table for page table value
554
555 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
556 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
557
558 // Read the descriptor from the first level page table
559 Descriptor = FirstLevelTable[FirstLevelIdx];
560
561 // Does this descriptor need to be converted from section entry to 4K pages?
562 if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {
563 Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
564 if (EFI_ERROR(Status)) {
565 // Exit for loop
566 break;
567 }
568
569 // Re-read descriptor
570 Descriptor = FirstLevelTable[FirstLevelIdx];
571 }
572
573 // Obtain page table base address
574 PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);
575
576 // Calculate index into the page table
577 PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
578 ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
579
580 // Get the entry
581 CurrentPageTableEntry = PageTable[PageTableIndex];
582
583 // Mask off appropriate fields
584 PageTableEntry = CurrentPageTableEntry & ~EntryMask;
585
586 // Mask in new attributes and/or permissions
587 PageTableEntry |= EntryValue;
588
589 if (VirtualMask != 0) {
590 // Make this virtual address point at a physical page
591 PageTableEntry &= ~VirtualMask;
592 }
593
594 if (CurrentPageTableEntry != PageTableEntry) {
595 Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));
596 if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {
597 // The current section mapping is cacheable so Clean/Invalidate the MVA of the page
598 // Note assumes switch(Attributes), not ARMv7 possibilities
599 WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);
600 }
601
602 // Only need to update if we are changing the entry
603 PageTable[PageTableIndex] = PageTableEntry;
604 ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
605 }
606
607 Status = EFI_SUCCESS;
608 Offset += TT_DESCRIPTOR_PAGE_SIZE;
609
610 } // End first level translation table loop
611
612 return Status;
613 }
614
615
616
617 EFI_STATUS
618 UpdateSectionEntries (
619 IN EFI_PHYSICAL_ADDRESS BaseAddress,
620 IN UINT64 Length,
621 IN UINT64 Attributes,
622 IN EFI_PHYSICAL_ADDRESS VirtualMask
623 )
624 {
625 EFI_STATUS Status = EFI_SUCCESS;
626 UINT32 EntryMask;
627 UINT32 EntryValue;
628 UINT32 FirstLevelIdx;
629 UINT32 NumSections;
630 UINT32 i;
631 UINT32 CurrentDescriptor;
632 UINT32 Descriptor;
633 VOID *Mva;
634 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
635
636 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
637 // EntryValue: values at bit positions specified by EntryMask
638
639 // Make sure we handle a section range that is unmapped
640 EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;
641 EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
642
643 // Although the PI spec is unclear on this the GCD guarantees that only
644 // one Attribute bit is set at a time, so we can safely use a switch statement
645 switch(Attributes) {
646 case EFI_MEMORY_UC:
647 // modify cacheability attributes
648 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
649 if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
650 // map to strongly ordered
651 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
652 } else {
653 // map to normal non-cachable
654 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
655 }
656 break;
657
658 case EFI_MEMORY_WC:
659 // modify cacheability attributes
660 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
661 // map to normal non-cachable
662 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
663 break;
664
665 case EFI_MEMORY_WT:
666 // modify cacheability attributes
667 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
668 // write through with no-allocate
669 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
670 break;
671
672 case EFI_MEMORY_WB:
673 // modify cacheability attributes
674 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
675 // write back (with allocate)
676 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
677 break;
678
679 case EFI_MEMORY_WP:
680 case EFI_MEMORY_XP:
681 case EFI_MEMORY_RP:
682 case EFI_MEMORY_UCE:
683 // cannot be implemented UEFI definition unclear for ARM
684 // Cause a page fault if these ranges are accessed.
685 EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT;
686 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
687 break;
688
689
690 default:
691 return EFI_UNSUPPORTED;
692 }
693
694 // obtain page table base
695 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
696
697 // calculate index into first level translation table for start of modification
698 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
699 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
700
701 // calculate number of 1MB first level entries this applies to
702 NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;
703
704 // iterate through each descriptor
705 for(i=0; i<NumSections; i++) {
706 CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
707
708 // has this descriptor already been coverted to pages?
709 if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {
710 // forward this 1MB range to page table function instead
711 Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);
712 } else {
713 // still a section entry
714
715 // mask off appropriate fields
716 Descriptor = CurrentDescriptor & ~EntryMask;
717
718 // mask in new attributes and/or permissions
719 Descriptor |= EntryValue;
720 if (VirtualMask != 0) {
721 Descriptor &= ~VirtualMask;
722 }
723
724 if (CurrentDescriptor != Descriptor) {
725 Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
726 if ((CurrentDescriptor & TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) == TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) {
727 // The current section mapping is cacheable so Clean/Invalidate the MVA of the section
728 // Note assumes switch(Attributes), not ARMv7 possabilities
729 WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);
730 }
731
732 // Only need to update if we are changing the descriptor
733 FirstLevelTable[FirstLevelIdx + i] = Descriptor;
734 ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);
735 }
736
737 Status = EFI_SUCCESS;
738 }
739 }
740
741 return Status;
742 }
743
744 EFI_STATUS
745 ConvertSectionToPages (
746 IN EFI_PHYSICAL_ADDRESS BaseAddress
747 )
748 {
749 EFI_STATUS Status;
750 EFI_PHYSICAL_ADDRESS PageTableAddr;
751 UINT32 FirstLevelIdx;
752 UINT32 SectionDescriptor;
753 UINT32 PageTableDescriptor;
754 UINT32 PageDescriptor;
755 UINT32 Index;
756
757 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
758 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
759
760 DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
761
762 // obtain page table base
763 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
764
765 // calculate index into first level translation table for start of modification
766 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
767 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
768
769 // get section attributes and convert to page attributes
770 SectionDescriptor = FirstLevelTable[FirstLevelIdx];
771 PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
772 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(SectionDescriptor,0);
773 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(SectionDescriptor);
774 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(SectionDescriptor,0);
775 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(SectionDescriptor);
776 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(SectionDescriptor);
777
778 // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
779 Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);
780 if (EFI_ERROR(Status)) {
781 return Status;
782 }
783
784 PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;
785
786 // write the page table entries out
787 for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
788 PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;
789 }
790
791 // flush d-cache so descriptors make it back to uncached memory for subsequent table walks
792 WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, TT_DESCRIPTOR_PAGE_SIZE);
793
794 // formulate page table entry, Domain=0, NS=0
795 PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
796
797 // write the page table entry out, repalcing section entry
798 FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
799
800 return EFI_SUCCESS;
801 }
802
803
804
805 EFI_STATUS
806 SetMemoryAttributes (
807 IN EFI_PHYSICAL_ADDRESS BaseAddress,
808 IN UINT64 Length,
809 IN UINT64 Attributes,
810 IN EFI_PHYSICAL_ADDRESS VirtualMask
811 )
812 {
813 EFI_STATUS Status;
814
815 if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
816 // Is the base and length a multiple of 1 MB?
817 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
818 Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);
819 } else {
820 // Base and/or length is not a multiple of 1 MB
821 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
822 Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);
823 }
824
825 // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
826 // flush and invalidate pages
827 //TODO: Do we really need to invalidate the caches everytime we change the memory attributes ?
828 ArmCleanInvalidateDataCache ();
829
830 ArmInvalidateInstructionCache ();
831
832 // Invalidate all TLB entries so changes are synced
833 ArmInvalidateTlb ();
834
835 return Status;
836 }
837
838
839 /**
840 This function modifies the attributes for the memory region specified by BaseAddress and
841 Length from their current attributes to the attributes specified by Attributes.
842
843 @param This The EFI_CPU_ARCH_PROTOCOL instance.
844 @param BaseAddress The physical address that is the start address of a memory region.
845 @param Length The size in bytes of the memory region.
846 @param Attributes The bit mask of attributes to set for the memory region.
847
848 @retval EFI_SUCCESS The attributes were set for the memory region.
849 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
850 BaseAddress and Length cannot be modified.
851 @retval EFI_INVALID_PARAMETER Length is zero.
852 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
853 the memory resource range.
854 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
855 resource range specified by BaseAddress and Length.
856 The bit mask of attributes is not support for the memory resource
857 range specified by BaseAddress and Length.
858
859 **/
860 EFI_STATUS
861 EFIAPI
862 CpuSetMemoryAttributes (
863 IN EFI_CPU_ARCH_PROTOCOL *This,
864 IN EFI_PHYSICAL_ADDRESS BaseAddress,
865 IN UINT64 Length,
866 IN UINT64 Attributes
867 )
868 {
869 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));
870 if ( ((BaseAddress & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0) || ((Length & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0)){
871 // minimum granularity is SIZE_4KB (4KB on ARM)
872 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));
873 return EFI_UNSUPPORTED;
874 }
875
876 return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);
877 }
878
879
880
881 //
882 // Add a new protocol to support
883 //
884
885 EFI_STATUS
886 EFIAPI
887 CpuConvertPagesToUncachedVirtualAddress (
888 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,
889 IN EFI_PHYSICAL_ADDRESS Address,
890 IN UINTN Length,
891 IN EFI_PHYSICAL_ADDRESS VirtualMask,
892 OUT UINT64 *Attributes OPTIONAL
893 )
894 {
895 EFI_STATUS Status;
896 EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
897
898
899 if (Attributes != NULL) {
900 Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);
901 if (!EFI_ERROR (Status)) {
902 *Attributes = GcdDescriptor.Attributes;
903 }
904 }
905
906 //
907 // Make this address range page fault if accessed. If it is a DMA buffer than this would
908 // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask
909 // to that address.
910 //
911 Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);
912 if (!EFI_ERROR (Status)) {
913 Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);
914 }
915
916 DEBUG ((DEBUG_INFO | DEBUG_LOAD, "ConvertPagesToUncachedVirtualAddress()\n Unmapped 0x%08lx Mapped 0x%08lx 0x%x bytes\n", Address, Address | VirtualMask, Length));
917
918 return Status;
919 }
920
921
922 EFI_STATUS
923 EFIAPI
924 CpuReconvertPages (
925 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,
926 IN EFI_PHYSICAL_ADDRESS Address,
927 IN UINTN Length,
928 IN EFI_PHYSICAL_ADDRESS VirtualMask,
929 IN UINT64 Attributes
930 )
931 {
932 EFI_STATUS Status;
933
934 DEBUG ((DEBUG_INFO | DEBUG_LOAD, "CpuReconvertPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));
935
936 //
937 // Unmap the alaised Address
938 //
939 Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);
940 if (!EFI_ERROR (Status)) {
941 //
942 // Restore atttributes
943 //
944 Status = SetMemoryAttributes (Address, Length, Attributes, 0);
945 }
946
947 return Status;
948 }
949
950
951 VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {
952 CpuConvertPagesToUncachedVirtualAddress,
953 CpuReconvertPages
954 };
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