3 Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
4 Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.<BR>
5 Copyright (c) 2011, ARM Limited. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 PEIM to provide fake memory init
28 // The package level header files this module uses
32 // The protocols, PPI and GUID defintions for this module
34 #include <Ppi/ArmMpCoreInfo.h>
37 // The Library classes this module consumes
39 #include <Library/DebugLib.h>
40 #include <Library/PeimEntryPoint.h>
41 #include <Library/PeiServicesLib.h>
42 #include <Library/PcdLib.h>
43 #include <Library/HobLib.h>
44 #include <Library/ArmLib.h>
50 #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
51 #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
55 OUT UINT32
*PhysicalBase
,
59 EFI_PEI_HOB_POINTERS NextHob
;
61 // Look at the resource descriptor hobs, choose the first system memory one
62 NextHob
.Raw
= GetHobList ();
63 while ((NextHob
.Raw
= GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR
, NextHob
.Raw
)) != NULL
) {
64 if(NextHob
.ResourceDescriptor
->ResourceType
== EFI_RESOURCE_SYSTEM_MEMORY
)
66 *PhysicalBase
= (UINT32
)NextHob
.ResourceDescriptor
->PhysicalStart
;
67 *Length
= (UINT32
)NextHob
.ResourceDescriptor
->ResourceLength
;
71 NextHob
.Raw
= GET_NEXT_HOB (NextHob
);
84 UINT32 CacheAttributes
;
85 UINT32 SystemMemoryBase
;
86 UINT32 SystemMemoryLength
;
87 UINT32 SystemMemoryLastAddress
;
88 ARM_MEMORY_REGION_DESCRIPTOR MemoryTable
[4];
89 VOID
*TranslationTableBase
;
90 UINTN TranslationTableSize
;
92 if (FeaturePcdGet(PcdCacheEnable
) == TRUE
) {
93 CacheAttributes
= DDR_ATTRIBUTES_CACHED
;
95 CacheAttributes
= DDR_ATTRIBUTES_UNCACHED
;
101 Status
= FindMainMemory (&SystemMemoryBase
, &SystemMemoryLength
);
102 ASSERT_EFI_ERROR (Status
);
104 SystemMemoryLastAddress
= SystemMemoryBase
+ (SystemMemoryLength
-1);
106 // If system memory does not begin at 0
107 if(SystemMemoryBase
> 0) {
108 MemoryTable
[Idx
].PhysicalBase
= 0;
109 MemoryTable
[Idx
].VirtualBase
= 0;
110 MemoryTable
[Idx
].Length
= SystemMemoryBase
;
111 MemoryTable
[Idx
].Attributes
= ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
;
115 MemoryTable
[Idx
].PhysicalBase
= SystemMemoryBase
;
116 MemoryTable
[Idx
].VirtualBase
= SystemMemoryBase
;
117 MemoryTable
[Idx
].Length
= SystemMemoryLength
;
118 MemoryTable
[Idx
].Attributes
= (ARM_MEMORY_REGION_ATTRIBUTES
)CacheAttributes
;
121 // If system memory does not go to the last address (0xFFFFFFFF)
122 if( SystemMemoryLastAddress
< MAX_ADDRESS
) {
123 MemoryTable
[Idx
].PhysicalBase
= SystemMemoryLastAddress
+ 1;
124 MemoryTable
[Idx
].VirtualBase
= MemoryTable
[Idx
].PhysicalBase
;
125 MemoryTable
[Idx
].Length
= MAX_ADDRESS
- MemoryTable
[Idx
].PhysicalBase
+ 1;
126 MemoryTable
[Idx
].Attributes
= ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
;
131 MemoryTable
[Idx
].PhysicalBase
= 0;
132 MemoryTable
[Idx
].VirtualBase
= 0;
133 MemoryTable
[Idx
].Length
= 0;
134 MemoryTable
[Idx
].Attributes
= (ARM_MEMORY_REGION_ATTRIBUTES
)0;
136 DEBUG ((EFI_D_INFO
, "Enabling MMU, setting 0x%08x + %d MB to %a\n",
137 SystemMemoryBase
, SystemMemoryLength
/1024/1024,
138 (CacheAttributes
== DDR_ATTRIBUTES_CACHED
) ? "cacheable" : "uncacheable"));
140 ArmConfigureMmu (MemoryTable
, &TranslationTableBase
, &TranslationTableSize
);
142 BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS
)(UINTN
)TranslationTableBase
, TranslationTableSize
, EfiBootServicesData
);
153 FileHandle - Handle of the file being invoked.
154 PeiServices - Describes the list of possible PEI Services.
158 Status - EFI_SUCCESS if the boot mode could be set
164 IN EFI_PEI_FILE_HANDLE FileHandle
,
165 IN CONST EFI_PEI_SERVICES
**PeiServices
169 ARM_MP_CORE_INFO_PPI
*ArmMpCoreInfoPpi
;
171 ARM_CORE_INFO
*ArmCoreInfoTable
;
173 // Enable program flow prediction, if supported.
174 ArmEnableBranchPrediction ();
176 // Publish the CPU memory and io spaces sizes
177 BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize
), PcdGet8 (PcdPrePiCpuIoSize
));
181 // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
182 Status
= PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid
, 0, NULL
, (VOID
**)&ArmMpCoreInfoPpi
);
183 if (!EFI_ERROR(Status
)) {
184 // Build the MP Core Info Table
186 Status
= ArmMpCoreInfoPpi
->GetMpCoreInfo (&ArmCoreCount
, &ArmCoreInfoTable
);
187 if (!EFI_ERROR(Status
) && (ArmCoreCount
> 0)) {
188 // Build MPCore Info HOB
189 BuildGuidDataHob (&gArmMpCoreInfoGuid
, ArmCoreInfoTable
, sizeof (ARM_CORE_INFO
) * ArmCoreCount
);