2 This file implement the MMC Host Protocol for the ARM PrimeCell PL180.
4 Copyright (c) 2011, ARM Limited. All rights reserved.
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Library/DevicePathLib.h>
19 #include <Library/BaseMemoryLib.h>
21 EFI_MMC_HOST_PROTOCOL
*gpMmcHost
;
26 #define MMCI0_BLOCKLEN 512
27 #define MMCI0_POW2_BLOCKLEN 9
28 #define MMCI0_TIMEOUT 1000
35 return ((MmioRead32(MCI_POWER_CONTROL_REG
) & 0x3) == MCI_POWER_ON
);
43 MCI_TRACE("MciInitialize()");
52 return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress
)) & 1);
60 return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress
)) & 2);
64 //Note: This function has been commented out because it is not used yet.
65 // This function could be used to remove the hardcoded BlockLen used
66 // in MciPrepareDataPath
68 // Convert block size to 2^n
81 Loop
= (Loop
>> 1) & 0xFFFF;
83 } while (Pow2BlockLen
&& (!(Loop
& BlockLen
)));
91 IN UINTN TransferDirection
94 // Set Data Length & Data Timer
95 MmioWrite32(MCI_DATA_TIMER_REG
,0xFFFFFFF);
96 MmioWrite32(MCI_DATA_LENGTH_REG
,MMCI0_BLOCKLEN
);
99 //Note: we are using a hardcoded BlockLen (=512). If we decide to use a variable size, we could
100 // compute the pow2 of BlockLen with the above function GetPow2BlockLen()
101 MmioWrite32(MCI_DATA_CTL_REG
, MCI_DATACTL_ENABLE
| MCI_DATACTL_DMA_ENABLE
| TransferDirection
| (MMCI0_POW2_BLOCKLEN
<< 4));
103 MmioWrite32(MCI_DATA_CTL_REG
, MCI_DATACTL_ENABLE
| MCI_DATACTL_DMA_ENABLE
| TransferDirection
| MCI_DATACTL_STREAM_TRANS
);
118 RetVal
= EFI_SUCCESS
;
120 if ((MmcCmd
== MMC_CMD17
) || (MmcCmd
== MMC_CMD11
)) {
121 MciPrepareDataPath(MCI_DATACTL_CARD_TO_CONT
);
122 } else if ((MmcCmd
== MMC_CMD24
) || (MmcCmd
== MMC_CMD20
)) {
123 MciPrepareDataPath(MCI_DATACTL_CONT_TO_CARD
);
126 // Create Command for PL180
127 Cmd
= (MMC_GET_INDX(MmcCmd
) & INDX_MASK
) | MCI_CPSM_ENABLED
;
128 if (MmcCmd
& MMC_CMD_WAIT_RESPONSE
) {
129 Cmd
|= MCI_CPSM_WAIT_RESPONSE
;
132 if (MmcCmd
& MMC_CMD_LONG_RESPONSE
) {
133 Cmd
|= MCI_CPSM_LONG_RESPONSE
;
136 // Clear Status register static flags
137 MmioWrite32(MCI_CLEAR_STATUS_REG
,0x7FF);
139 //Write to command argument register
140 MmioWrite32(MCI_ARGUMENT_REG
,Argument
);
142 //Write to command register
143 MmioWrite32(MCI_COMMAND_REG
,Cmd
);
145 if (Cmd
& MCI_CPSM_WAIT_RESPONSE
) {
146 Status
= MmioRead32(MCI_STATUS_REG
);
147 while (!(Status
& (MCI_STATUS_CMD_RESPEND
| MCI_STATUS_CMD_CMDCRCFAIL
| MCI_STATUS_CMD_CMDTIMEOUT
| MCI_STATUS_CMD_START_BIT_ERROR
))) {
148 Status
= MmioRead32(MCI_STATUS_REG
);
151 if ((Status
& MCI_STATUS_CMD_START_BIT_ERROR
)) {
152 DEBUG ((EFI_D_ERROR
, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd
& 0x3F),MmioRead32(MCI_RESPONSE0_REG
),Status
));
153 RetVal
= EFI_NO_RESPONSE
;
155 } else if ((Status
& MCI_STATUS_CMD_CMDTIMEOUT
)) {
156 //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));
157 RetVal
= EFI_TIMEOUT
;
159 } else if ((!(MmcCmd
& MMC_CMD_NO_CRC_RESPONSE
)) && (Status
& MCI_STATUS_CMD_CMDCRCFAIL
)) {
160 // The CMD1 and response type R3 do not contain CRC. We should ignore the CRC failed Status.
161 RetVal
= EFI_CRC_ERROR
;
164 RetVal
= EFI_SUCCESS
;
168 Status
= MmioRead32(MCI_STATUS_REG
);
169 while (!(Status
& (MCI_STATUS_CMD_SENT
| MCI_STATUS_CMD_CMDCRCFAIL
| MCI_STATUS_CMD_CMDTIMEOUT
| MCI_STATUS_CMD_START_BIT_ERROR
))) {
170 Status
= MmioRead32(MCI_STATUS_REG
);
173 if ((Status
& MCI_STATUS_CMD_START_BIT_ERROR
)) {
174 DEBUG ((EFI_D_ERROR
, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd
& 0x3F),MmioRead32(MCI_RESPONSE0_REG
),Status
));
175 RetVal
= EFI_NO_RESPONSE
;
177 } else if ((Status
& MCI_STATUS_CMD_CMDTIMEOUT
)) {
178 //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));
179 RetVal
= EFI_TIMEOUT
;
182 if ((!(MmcCmd
& MMC_CMD_NO_CRC_RESPONSE
)) && (Status
& MCI_STATUS_CMD_CMDCRCFAIL
)) {
183 // The CMD1 does not contain CRC. We should ignore the CRC failed Status.
184 RetVal
= EFI_CRC_ERROR
;
187 RetVal
= EFI_SUCCESS
;
193 //Disable Command Path
194 CmdCtrlReg
= MmioRead32(MCI_COMMAND_REG
);
195 MmioWrite32(MCI_COMMAND_REG
, (CmdCtrlReg
& ~MCI_CPSM_ENABLED
));
201 IN MMC_RESPONSE_TYPE Type
,
205 if (Buffer
== NULL
) {
206 return EFI_INVALID_PARAMETER
;
209 if ((Type
== MMC_RESPONSE_TYPE_R1
) || (Type
== MMC_RESPONSE_TYPE_R1b
) ||
210 (Type
== MMC_RESPONSE_TYPE_R3
) || (Type
== MMC_RESPONSE_TYPE_R6
) ||
211 (Type
== MMC_RESPONSE_TYPE_R7
))
213 Buffer
[0] = MmioRead32(MCI_RESPONSE0_REG
);
214 Buffer
[1] = MmioRead32(MCI_RESPONSE1_REG
);
215 } else if (Type
== MMC_RESPONSE_TYPE_R2
) {
216 Buffer
[0] = MmioRead32(MCI_RESPONSE0_REG
);
217 Buffer
[1] = MmioRead32(MCI_RESPONSE1_REG
);
218 Buffer
[2] = MmioRead32(MCI_RESPONSE2_REG
);
219 Buffer
[3] = MmioRead32(MCI_RESPONSE3_REG
);
238 RetVal
= EFI_SUCCESS
;
240 // Read data from the RX FIFO
242 Finish
= MMCI0_BLOCKLEN
/ 4;
244 // Read the Status flags
245 Status
= MmioRead32(MCI_STATUS_REG
);
247 // Do eight reads if possible else a single read
248 if (Status
& MCI_STATUS_CMD_RXFIFOHALFFULL
) {
249 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
251 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
253 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
255 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
257 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
259 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
261 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
263 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
265 } else if (Status
& MCI_STATUS_CMD_RXDATAAVAILBL
) {
266 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
269 //Check for error conditions and timeouts
270 if(Status
& MCI_STATUS_CMD_DATATIMEOUT
) {
271 DEBUG ((EFI_D_ERROR
, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
));
272 RetVal
= EFI_TIMEOUT
;
274 } else if(Status
& MCI_STATUS_CMD_DATACRCFAIL
) {
275 DEBUG ((EFI_D_ERROR
, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
));
276 RetVal
= EFI_CRC_ERROR
;
278 } else if(Status
& MCI_STATUS_CMD_START_BIT_ERROR
) {
279 DEBUG ((EFI_D_ERROR
, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
));
280 RetVal
= EFI_NO_RESPONSE
;
284 //clear RX over run flag
285 if(Status
& MCI_STATUS_CMD_RXOVERRUN
) {
286 MmioWrite32(MCI_CLEAR_STATUS_REG
, MCI_STATUS_CMD_RXOVERRUN
);
288 } while ((Loop
< Finish
));
291 MmioWrite32(MCI_CLEAR_STATUS_REG
, 0x7FF);
294 DataCtrlReg
= MmioRead32(MCI_DATA_CTL_REG
);
295 MmioWrite32(MCI_DATA_CTL_REG
, (DataCtrlReg
& 0xFE));
314 RetVal
= EFI_SUCCESS
;
316 // Write the data to the TX FIFO
318 Finish
= MMCI0_BLOCKLEN
/ 4;
319 Timer
= MMCI0_TIMEOUT
* 100;
321 // Read the Status flags
322 Status
= MmioRead32(MCI_STATUS_REG
);
324 // Do eight writes if possible else a single write
325 if (Status
& MCI_STATUS_CMD_TXFIFOHALFEMPTY
) {
326 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
328 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
330 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
332 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
334 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
336 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
338 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
340 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
342 } else if ((Status
& MCI_STATUS_CMD_TXFIFOEMPTY
)) {
343 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
346 //Check for error conditions and timeouts
347 if(Status
& MCI_STATUS_CMD_DATATIMEOUT
) {
348 DEBUG ((EFI_D_ERROR
, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
));
349 RetVal
= EFI_TIMEOUT
;
351 } else if(Status
& MCI_STATUS_CMD_DATACRCFAIL
) {
352 DEBUG ((EFI_D_ERROR
, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
));
353 RetVal
= EFI_CRC_ERROR
;
355 } else if(Status
& MCI_STATUS_CMD_TX_UNDERRUN
) {
356 DEBUG ((EFI_D_ERROR
, "MciWriteBlockData(): TX buffer Underrun! Response:0x%X Status:0x%x, Number of bytes written 0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
, Loop
));
357 RetVal
= EFI_BUFFER_TOO_SMALL
;
362 } while (Loop
< Finish
);
364 // Wait for FIFO to drain
365 Timer
= MMCI0_TIMEOUT
* 60;
366 Status
= MmioRead32(MCI_STATUS_REG
);
369 while (((Status
& MCI_STATUS_CMD_TXDONE
) != MCI_STATUS_CMD_TXDONE
) && Timer
) {
372 while (((Status
& MCI_STATUS_CMD_DATAEND
) != MCI_STATUS_CMD_DATAEND
) && Timer
) {
375 Status
= MmioRead32(MCI_STATUS_REG
);
380 DEBUG ((EFI_D_ERROR
, "MciWriteBlockData(): Data End timeout Number of bytes written 0x%x\n",Loop
));
386 MmioWrite32(MCI_CLEAR_STATUS_REG
, 0x7FF);
388 RetVal
= EFI_TIMEOUT
;
393 DataCtrlReg
= MmioRead32(MCI_DATA_CTL_REG
);
394 MmioWrite32(MCI_DATA_CTL_REG
, (DataCtrlReg
& 0xFE));
406 case MmcInvalidState
:
409 case MmcHwInitializationState
:
410 // If device already turn on then restart it
411 Data32
= MmioRead32(MCI_POWER_CONTROL_REG
);
412 if ((Data32
& 0x2) == MCI_POWER_UP
) {
413 MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOff MCI");
416 MmioWrite32(MCI_CLOCK_CONTROL_REG
, 0);
417 MmioWrite32(MCI_POWER_CONTROL_REG
, 0);
418 MicroSecondDelay(100);
421 MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOn MCI");
423 // - 0x1D = 29 => should be the clock divider to be less than 400kHz at MCLK = 24Mhz
424 MmioWrite32(MCI_CLOCK_CONTROL_REG
,0x1D | MCI_CLOCK_ENABLE
| MCI_CLOCK_POWERSAVE
);
425 //MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE);
428 MmioWrite32(MCI_POWER_CONTROL_REG
,MCI_POWER_OPENDRAIN
| (15<<2));
429 MmioWrite32(MCI_POWER_CONTROL_REG
,MCI_POWER_ROD
| MCI_POWER_OPENDRAIN
| (15<<2) | MCI_POWER_UP
);
430 MicroSecondDelay(10);
431 MmioWrite32(MCI_POWER_CONTROL_REG
,MCI_POWER_ROD
| MCI_POWER_OPENDRAIN
| (15<<2) | MCI_POWER_ON
);
432 MicroSecondDelay(100);
434 // Set Data Length & Data Timer
435 MmioWrite32(MCI_DATA_TIMER_REG
,0xFFFFF);
436 MmioWrite32(MCI_DATA_LENGTH_REG
,8);
438 ASSERT((MmioRead32(MCI_POWER_CONTROL_REG
) & 0x3) == MCI_POWER_ON
);
441 MCI_TRACE("MciNotifyState(MmcIdleState)");
444 MCI_TRACE("MciNotifyState(MmcReadyState)");
446 case MmcIdentificationState
:
447 MCI_TRACE("MciNotifyState(MmcIdentificationState)");
449 case MmcStandByState
:{
450 volatile UINT32 PwrCtrlReg
;
451 MCI_TRACE("MciNotifyState(MmcStandByState)");
453 // Enable MCICMD push-pull drive
454 PwrCtrlReg
= MmioRead32(MCI_POWER_CONTROL_REG
);
455 //Disable Open Drain output
456 PwrCtrlReg
&=~(MCI_POWER_OPENDRAIN
);
457 MmioWrite32(MCI_POWER_CONTROL_REG
,PwrCtrlReg
);
459 // Set MMCI0 clock to 4MHz (24MHz may be possible with cache enabled)
461 // Note: Increasing clock speed causes TX FIFO under-run errors.
462 // So careful when optimising this driver for higher performance.
464 MmioWrite32(MCI_CLOCK_CONTROL_REG
,0x02 | MCI_CLOCK_ENABLE
| MCI_CLOCK_POWERSAVE
);
465 // Set MMCI0 clock to 24MHz (by bypassing the divider)
466 //MmioWrite32(MCI_CLOCK_CONTROL_REG,MCI_CLOCK_BYPASS | MCI_CLOCK_ENABLE);
469 case MmcTransferState
:
470 //MCI_TRACE("MciNotifyState(MmcTransferState)");
472 case MmcSendingDataState
:
473 MCI_TRACE("MciNotifyState(MmcSendingDataState)");
475 case MmcReceiveDataState
:
476 MCI_TRACE("MciNotifyState(MmcReceiveDataState)");
478 case MmcProgrammingState
:
479 MCI_TRACE("MciNotifyState(MmcProgrammingState)");
481 case MmcDisconnectState
:
482 MCI_TRACE("MciNotifyState(MmcDisconnectState)");
490 EFI_GUID mPL180MciDevicePathGuid
= EFI_CALLER_ID_GUID
;
494 IN EFI_DEVICE_PATH_PROTOCOL
**DevicePath
497 EFI_DEVICE_PATH_PROTOCOL
*NewDevicePathNode
;
499 NewDevicePathNode
= CreateDeviceNode(HARDWARE_DEVICE_PATH
,HW_VENDOR_DP
,sizeof(VENDOR_DEVICE_PATH
));
500 CopyGuid(&((VENDOR_DEVICE_PATH
*)NewDevicePathNode
)->Guid
,&mPL180MciDevicePathGuid
);
502 *DevicePath
= NewDevicePathNode
;
506 EFI_MMC_HOST_PROTOCOL gMciHost
= {
518 PL180MciDxeInitialize (
519 IN EFI_HANDLE ImageHandle
,
520 IN EFI_SYSTEM_TABLE
*SystemTable
524 EFI_HANDLE Handle
= NULL
;
526 MCI_TRACE("PL180MciDxeInitialize()");
528 //Publish Component Name, BlockIO protocol interfaces
529 Status
= gBS
->InstallMultipleProtocolInterfaces (
531 &gEfiMmcHostProtocolGuid
, &gMciHost
,
534 ASSERT_EFI_ERROR (Status
);