2 // Copyright (c) 2011, ARM Limited. All rights reserved.
4 // This program and the accompanying materials
5 // are licensed and made available under the terms and conditions of the BSD License
6 // which accompanies this distribution. The full text of the license may be found at
7 // http://opensource.org/licenses/bsd-license.php
9 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #include <AsmMacroIoLib.h>
15 #include <Library/PcdLib.h>
18 INCLUDE AsmMacroIoLib.inc
23 AREA ModuleInitializeSMC, CODE, READONLY
25 // Static memory configuation definitions for SMC
30 // CS0 CS0-Interf0 NOR1 flash on the motherboard
31 // CS1 CS1-Interf0 Reserved for the motherboard
32 // CS2 CS2-Interf0 SRAM on the motherboard
33 // CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard
34 // CS4 CS0-Interf1 NOR2 flash on the motherboard
35 // CS5 CS1-Interf1 memory-mapped peripherals
36 // CS6 CS2-Interf1 memory-mapped peripherals
37 // CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.
40 // IN r2 VideoSRamBase
41 // NOTE: This code is been called before any stack has been setup. It means some registers
42 // could be overwritten (case of 'r0')
45 // Setup NOR1 (CS0-Interface0)
48 //Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
49 //Read cycle timeout = 0xA (0:3)
50 //Write cycle timeout = 0x3(7:4)
51 //OE Assertion Delay = 0x9(11:8)
52 //WE Assertion delay = 0x3(15:12)
53 //Page cycle timeout = 0x2(19:16)
55 str r0, [r1, #SmcSetCycles]
57 //Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
58 // 0x00000002 = MemoryWidth: 32bit
59 // 0x00000028 = ReadMemoryBurstLength:continuous
60 // 0x00000280 = WriteMemoryBurstLength:continuous
61 // 0x00000800 = Set Address Valid
63 str r0, [r1, #SmcSetOpMode]
65 //Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
66 // 0x00000000 = ChipSelect0-Interface 0
67 // 0x00400000 = CmdTypes: UpdateRegs
69 str r0, [r1, #SmcDirectCmd]
72 // Setup SRAM (CS2-Interface0)
75 str r0, [r1, #SmcSetCycles]
77 // 0x00000002 = MemoryWidth: 32bit
78 // 0x00000800 = Set Address Valid
80 str r0, [r1, #SmcSetOpMode]
82 // 0x01000000 = ChipSelect2-Interface 0
83 // 0x00400000 = CmdTypes: UpdateRegs
85 str r0, [r1, #SmcDirectCmd]
88 // USB/Eth/VRAM (CS3-Interface0)
91 str r0, [r1, #SmcSetCycles]
93 // 0x00000002 = MemoryWidth: 32bit
94 // 0x00000004 = Memory reads are synchronous
95 // 0x00000040 = Memory writes are synchronous
97 str r0, [r1, #SmcSetOpMode]
99 // 0x01800000 = ChipSelect3-Interface 0
100 // 0x00400000 = CmdTypes: UpdateRegs
102 str r0, [r1, #SmcDirectCmd]
105 // Setup NOR3 (CS0-Interface1)
108 str r0, [r1, #SmcSetCycles]
110 // 0x00000002 = MemoryWidth: 32bit
111 // 0x00000028 = ReadMemoryBurstLength:continuous
112 // 0x00000280 = WriteMemoryBurstLength:continuous
113 // 0x00000800 = Set Address Valid
115 str r0, [r1, #SmcSetOpMode]
117 // 0x02000000 = ChipSelect0-Interface 1
118 // 0x00400000 = CmdTypes: UpdateRegs
120 str r0, [r1, #SmcDirectCmd]
123 // Setup Peripherals (CS3-Interface1)
126 str r0, [r1, #SmcSetCycles]
128 // 0x00000002 = MemoryWidth: 32bit
129 // 0x00000004 = Memory reads are synchronous
130 // 0x00000040 = Memory writes are synchronous
132 str r0, [r1, #SmcSetOpMode]
134 // 0x03800000 = ChipSelect3-Interface 1
135 // 0x00400000 = CmdTypes: UpdateRegs
137 str r0, [r1, #SmcDirectCmd]
140 // Setup VRAM (CS1-Interface0)
143 str r0, [r1, #SmcSetCycles]
145 // 0x00000002 = MemoryWidth: 32bit
146 // 0x00000004 = Memory reads are synchronous
147 // 0x00000040 = Memory writes are synchronous
149 str r0, [r1, #SmcSetOpMode]
151 // 0x00800000 = ChipSelect1-Interface 0
152 // 0x00400000 = CmdTypes: UpdateRegs
154 str r0, [r1, #SmcDirectCmd]
157 // Page mode setup for VRAM
174 //confirm page mode enabled