ArmPkg/Drivers/PL35xSmc/InitializeSMC.asm

   1 //
   2 //  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Library/PcdLib.h>
  16 #include <Drivers/PL354Smc.h>
  17 #include <AutoGen.h>
  18
  19   INCLUDE AsmMacroIoLib.inc
  20
  21   EXPORT  SMCInitializeNOR
  22   EXPORT  SMCInitializeSRAM
  23   EXPORT  SMCInitializePeripherals
  24   EXPORT  SMCInitializeVRAM
  25
  26   PRESERVE8
  27   AREA    ModuleInitializeSMC, CODE, READONLY
  28
  29 // CS0  CS0-Interf0     NOR1 flash on the motherboard
  30 // CS1  CS1-Interf0     Reserved for the motherboard
  31 // CS2  CS2-Interf0     SRAM on the motherboard
  32 // CS3  CS3-Interf0     memory-mapped Ethernet and USB controllers on the motherboard
  33 // CS4  CS0-Interf1     NOR2 flash on the motherboard
  34 // CS5  CS1-Interf1     memory-mapped peripherals
  35 // CS6  CS2-Interf1     memory-mapped peripherals
  36 // CS7  CS3-Interf1     system memory-mapped peripherals on the motherboard.
  37
  38 // IN r1 SmcBase
  39 // IN r2 ChipSelect
  40 // NOTE: This code is been called before any stack has been setup. It means some registers
  41 //       could be overwritten (case of 'r0')
  42 SMCInitializeNOR
  43   // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
  44   //   - Read cycle timeout  = 0xA (0:3)
  45   //   - Write cycle timeout = 0x3(7:4)
  46   //   - OE Assertion Delay  = 0x9(11:8)
  47   //   - WE Assertion delay  = 0x3(15:12)
  48   //   - Page cycle timeout  = 0x2(19:16)
  49   ldr     r0, = 0x0002393A
  50   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
  51
  52   // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
  53   ldr     r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)
  54   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
  55
  56   // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
  57   ldr     r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
  58   orr     r0, r0, r2
  59   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
  60
  61   bx    lr
  62
  63
  64 //
  65 // Setup SRAM (CS2-Interface0)
  66 //
  67 SMCInitializeSRAM
  68   ldr     r0, = 0x00027158
  69   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
  70
  71   ldr     r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)
  72   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
  73
  74   ldr     r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))
  75   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
  76
  77   bx    lr
  78
  79 SMCInitializePeripherals
  80 //
  81 // USB/Eth/VRAM (CS3-Interface0)
  82 //
  83   ldr     r0, = 0x000CD2AA
  84   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
  85
  86   ldr     r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
  87   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
  88
  89   ldr     r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))
  90   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
  91
  92
  93 //
  94 // Setup Peripherals (CS3-Interface1)
  95 //
  96   ldr     r0, = 0x00025156
  97   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
  98
  99   ldr     r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
 100   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
 101
 102   ldr     r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))
 103   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
 104
 105   bx    lr
 106
 107
 108 // IN r1 SmcBase
 109 // IN r2 VideoSRamBase
 110 // NOTE: This code is been called before any stack has been setup. It means some registers
 111 //       could be overwritten (case of 'r0')
 112 SMCInitializeVRAM
 113   //
 114   // Setup VRAM (CS1-Interface0)
 115   //
 116   ldr     r0, =  0x00049249
 117   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
 118
 119   ldr     r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
 120   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
 121
 122   ldr     r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))
 123   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
 124
 125   //
 126   // Page mode setup for VRAM
 127   //
 128
 129   // Read current state
 130   ldr     r0, [r2, #0]
 131   ldr     r0, [r2, #0]
 132   ldr     r0, = 0x00000000
 133   str     r0, [r2, #0]
 134   ldr     r0, [r2, #0]
 135
 136   // Enable page mode
 137   ldr     r0, [r2, #0]
 138   ldr     r0, [r2, #0]
 139   ldr     r0, = 0x00000000
 140   str     r0, [r2, #0]
 141   ldr     r0, = 0x00900090
 142   str     r0, [r2, #0]
 143
 144   // Confirm page mode enabled
 145   ldr     r0, [r2, #0]
 146   ldr     r0, [r2, #0]
 147   ldr     r0, = 0x00000000
 148   str     r0, [r2, #0]
 149   ldr     r0, [r2, #0]
 150
 151   bx    lr
 152
 153   END