ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Uefi.h>
  16 #include <Library/IoLib.h>
  17 #include <Drivers/PL390Gic.h>
  18
  19
  20 VOID
  21 EFIAPI
  22 PL390GicEnableInterruptInterface (
  23   IN  INTN          GicInterruptInterfaceBase
  24   )
  25 {
  26   /*
  27   * Enable the CPU interface in Non-Secure world
  28   * Note: The ICCICR register is banked when Security extensions are implemented
  29   */
  30   MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);
  31 }
  32
  33 VOID
  34 EFIAPI
  35 PL390GicEnableDistributor (
  36   IN  INTN          GicDistributorBase
  37   )
  38 {
  39   /*
  40    * Enable GIC distributor in Non-Secure world.
  41    * Note: The ICDDCR register is banked when Security extensions are implemented
  42    */
  43   MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001);
  44 }
  45
  46 VOID
  47 EFIAPI
  48 PL390GicSendSgiTo (
  49   IN  INTN          GicDistributorBase,
  50   IN  INTN          TargetListFilter,
  51   IN  INTN          CPUTargetList
  52   )
  53 {
  54   MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
  55 }
  56
  57 UINT32
  58 EFIAPI
  59 PL390GicAcknowledgeSgiFrom (
  60   IN  INTN          GicInterruptInterfaceBase,
  61   IN  INTN          CoreId
  62   )
  63 {
  64   INTN            InterruptId;
  65
  66   InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR);
  67
  68   // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
  69   if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
  70     // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
  71     MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
  72     return 1;
  73   } else {
  74     return 0;
  75   }
  76 }
  77
  78 UINT32
  79 EFIAPI
  80 PL390GicAcknowledgeSgi2From (
  81   IN  INTN          GicInterruptInterfaceBase,
  82   IN  INTN          CoreId,
  83   IN  INTN          SgiId
  84   )
  85 {
  86   INTN            InterruptId;
  87
  88   InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
  89
  90   // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
  91   if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
  92     // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
  93     MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
  94     return 1;
  95   } else {
  96     return 0;
  97   }
  98 }