57ae14150e7e4734d2bb455d2b71acd8b9f32f7c
[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c
1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Uefi.h>
16 #include <Library/IoLib.h>
17 #include <Library/ArmGicLib.h>
18
19 /*
20 * This function configures the all interrupts to be Non-secure.
21 *
22 */
23 VOID
24 EFIAPI
25 ArmGicSetupNonSecure (
26 IN INTN GicDistributorBase,
27 IN INTN GicInterruptInterfaceBase
28 )
29 {
30 UINTN InterruptId;
31 UINTN CachedPriorityMask;
32
33 CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
34
35 // Set priority Mask so that no interrupts get through to CPU
36 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
37
38 // Check if there are any pending interrupts
39 //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
40 while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
41 // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
42 InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
43
44 // Write to End of interrupt signal
45 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
46 }
47
48 // Ensure all GIC interrupts are Non-Secure
49 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
50 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
51 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
52
53 // Ensure all interrupts can get through the priority mask
54 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
55 }
56
57 VOID
58 EFIAPI
59 ArmGicEnableInterruptInterface (
60 IN INTN GicInterruptInterfaceBase
61 )
62 {
63 // Set Priority Mask to allow interrupts
64 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
65
66 // Enable CPU interface in Secure world
67 // Enable CPU inteface in Non-secure World
68 // Signal Secure Interrupts to CPU using FIQ line *
69 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
70 ARM_GIC_ICCICR_ENABLE_SECURE |
71 ARM_GIC_ICCICR_ENABLE_NS |
72 ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
73 }
74
75 VOID
76 EFIAPI
77 ArmGicEnableDistributor (
78 IN INTN GicDistributorBase
79 )
80 {
81 // Turn on the GIC distributor
82 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
83 }