ArmPkg/Drivers/PL390Gic/PL390GicSec.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/DebugLib.h>
  18 #include <Library/IoLib.h>
  19 #include <Library/ArmGicLib.h>
  20
  21 /*
  22  * This function configures the all interrupts to be Non-secure.
  23  *
  24  */
  25 VOID
  26 EFIAPI
  27 ArmGicSetupNonSecure (
  28   IN  UINTN         MpId,
  29   IN  INTN          GicDistributorBase,
  30   IN  INTN          GicInterruptInterfaceBase
  31   )
  32 {
  33   UINTN InterruptId;
  34   UINTN CachedPriorityMask;
  35   UINTN Index;
  36
  37   CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
  38
  39   // Set priority Mask so that no interrupts get through to CPU
  40   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
  41
  42   InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
  43
  44   // Only try to clear valid interrupts. Ignore spurious interrupts.
  45   while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase))   {
  46     // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
  47     MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
  48
  49     // Next
  50     InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
  51   }
  52
  53   // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
  54   if (IS_PRIMARY_CORE(MpId)) {
  55     // Ensure all GIC interrupts are Non-Secure
  56     for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {
  57       MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
  58     }
  59   } else {
  60     // The secondary cores only set the Non Secure bit to their banked PPIs
  61     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
  62   }
  63
  64   // Ensure all interrupts can get through the priority mask
  65   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
  66 }
  67
  68 /*
  69  * This function configures the interrupts set by the mask to be secure.
  70  *
  71  */
  72 VOID
  73 EFIAPI
  74 ArmGicSetSecureInterrupts (
  75   IN  UINTN         GicDistributorBase,
  76   IN  UINTN*        GicSecureInterruptMask,
  77   IN  UINTN         GicSecureInterruptMaskSize
  78   )
  79 {
  80   UINTN  Index;
  81   UINT32 InterruptStatus;
  82
  83   // We must not have more interrupts defined by the mask than the number of available interrupts
  84   ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));
  85
  86   // Set all the interrupts defined by the mask as Secure
  87   for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
  88     InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
  89     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
  90   }
  91 }
  92
  93 VOID
  94 EFIAPI
  95 ArmGicEnableInterruptInterface (
  96   IN  INTN          GicInterruptInterfaceBase
  97   )
  98 {
  99   // Set Priority Mask to allow interrupts
 100   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
 101
 102   // Enable CPU interface in Secure world
 103   // Enable CPU interface in Non-secure World
 104   // Signal Secure Interrupts to CPU using FIQ line *
 105   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
 106       ARM_GIC_ICCICR_ENABLE_SECURE |
 107       ARM_GIC_ICCICR_ENABLE_NS |
 108       ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
 109 }
 110
 111 VOID
 112 EFIAPI
 113 ArmGicDisableInterruptInterface (
 114   IN  INTN          GicInterruptInterfaceBase
 115   )
 116 {
 117   UINT32    ControlValue;
 118
 119   // Disable CPU interface in Secure world and Non-secure World
 120   ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);
 121   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));
 122 }
 123
 124 VOID
 125 EFIAPI
 126 ArmGicEnableDistributor (
 127   IN  INTN          GicDistributorBase
 128   )
 129 {
 130   // Turn on the GIC distributor
 131   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
 132 }