ArmPkg/Include/Chipset/AArch64.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __AARCH64_H__
  17 #define __AARCH64_H__
  18
  19 #include <Chipset/AArch64Mmu.h>
  20 #include <Chipset/ArmArchTimer.h>
  21
  22 // ARM Interrupt ID in Exception Table
  23 #define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_AARCH64_IRQ
  24
  25 // CPACR - Coprocessor Access Control Register definitions
  26 #define CPACR_TTA_EN            (1UL << 28)
  27 #define CPACR_FPEN_EL1          (1UL << 20)
  28 #define CPACR_FPEN_FULL         (3UL << 20)
  29 #define CPACR_CP_FULL_ACCESS    0x300000
  30
  31 // Coprocessor Trap Register (CPTR)
  32 #define AARCH64_CPTR_TFP        (1 << 10)
  33
  34 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
  35 #define AARCH64_PFR0_FP         (0xF << 16)
  36 #define AARCH64_PFR0_GIC        (0xF << 24)
  37
  38 // SCR - Secure Configuration Register definitions
  39 #define SCR_NS                  (1 << 0)
  40 #define SCR_IRQ                 (1 << 1)
  41 #define SCR_FIQ                 (1 << 2)
  42 #define SCR_EA                  (1 << 3)
  43 #define SCR_FW                  (1 << 4)
  44 #define SCR_AW                  (1 << 5)
  45
  46 // MIDR - Main ID Register definitions
  47 #define ARM_CPU_TYPE_MASK       0xFFF
  48 #define ARM_CPU_TYPE_AEMv8      0xD0F
  49 #define ARM_CPU_TYPE_A53        0xD03
  50 #define ARM_CPU_TYPE_A57        0xD07
  51 #define ARM_CPU_TYPE_A15        0xC0F
  52 #define ARM_CPU_TYPE_A9         0xC09
  53 #define ARM_CPU_TYPE_A5         0xC05
  54
  55 #define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )
  56 #define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  57
  58 // Hypervisor Configuration Register
  59 #define ARM_HCR_FMO       BIT3
  60 #define ARM_HCR_IMO       BIT4
  61 #define ARM_HCR_AMO       BIT5
  62 #define ARM_HCR_TSC       BIT19
  63 #define ARM_HCR_TGE       BIT27
  64
  65 // Exception Syndrome Register
  66 #define AARCH64_ESR_EC(Ecr)    ((0x3F << 26) & (Ecr))
  67 #define AARCH64_ESR_ISS(Ecr)   ((0x1FFFFFF) & (Ecr))
  68
  69 #define AARCH64_ESR_EC_SMC32   (0x13 << 26)
  70 #define AARCH64_ESR_EC_SMC64   (0x17 << 26)
  71
  72 // AArch64 Exception Level
  73 #define AARCH64_EL3       0xC
  74 #define AARCH64_EL2       0x8
  75 #define AARCH64_EL1       0x4
  76
  77 // Saved Program Status Register definitions
  78 #define SPSR_A                  BIT8
  79 #define SPSR_I                  BIT7
  80 #define SPSR_F                  BIT6
  81
  82 #define SPSR_AARCH32            BIT4
  83
  84 #define SPSR_AARCH32_MODE_USER  0x0
  85 #define SPSR_AARCH32_MODE_FIQ   0x1
  86 #define SPSR_AARCH32_MODE_IRQ   0x2
  87 #define SPSR_AARCH32_MODE_SVC   0x3
  88 #define SPSR_AARCH32_MODE_ABORT 0x7
  89 #define SPSR_AARCH32_MODE_UNDEF 0xB
  90 #define SPSR_AARCH32_MODE_SYS   0xF
  91
  92 // Counter-timer Hypervisor Control register definitions
  93 #define CNTHCTL_EL2_EL1PCTEN    BIT0
  94 #define CNTHCTL_EL2_EL1PCEN     BIT1
  95
  96 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
  97
  98 VOID
  99 EFIAPI
 100 ArmEnableSWPInstruction (
 101   VOID
 102   );
 103
 104 UINTN
 105 EFIAPI
 106 ArmReadCbar (
 107   VOID
 108   );
 109
 110 UINTN
 111 EFIAPI
 112 ArmReadTpidrurw (
 113   VOID
 114   );
 115
 116 VOID
 117 EFIAPI
 118 ArmWriteTpidrurw (
 119   UINTN Value
 120   );
 121
 122 UINTN
 123 EFIAPI
 124 ArmGetTCR (
 125   VOID
 126   );
 127
 128 VOID
 129 EFIAPI
 130 ArmSetTCR (
 131   UINTN Value
 132   );
 133
 134 UINTN
 135 EFIAPI
 136 ArmGetMAIR (
 137   VOID
 138   );
 139
 140 VOID
 141 EFIAPI
 142 ArmSetMAIR (
 143   UINTN Value
 144   );
 145
 146 VOID
 147 EFIAPI
 148 ArmDisableAlignmentCheck (
 149   VOID
 150   );
 151
 152 VOID
 153 EFIAPI
 154 ArmEnableAlignmentCheck (
 155   VOID
 156   );
 157
 158 VOID
 159 EFIAPI
 160 ArmDisableAllExceptions (
 161   VOID
 162   );
 163
 164 VOID
 165 ArmWriteHcr (
 166   IN UINTN Hcr
 167   );
 168
 169 UINTN
 170 ArmReadCurrentEL (
 171   VOID
 172   );
 173
 174 UINT64
 175 PageAttributeToGcdAttribute (
 176   IN UINT64 PageAttributes
 177   );
 178
 179 UINT64
 180 GcdAttributeToPageAttribute (
 181   IN UINT64 GcdAttributes
 182   );
 183
 184 UINTN
 185 ArmWriteCptr (
 186   IN  UINT64 Cptr
 187   );
 188
 189 #endif // __AARCH64_H__