ArmPkg/Include/Chipset/AArch64.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __AARCH64_H__
  17 #define __AARCH64_H__
  18
  19 #include <Chipset/AArch64Mmu.h>
  20 #include <Chipset/ArmArchTimer.h>
  21
  22 // ARM Interrupt ID in Exception Table
  23 #define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_AARCH64_IRQ
  24
  25 // CPACR - Coprocessor Access Control Register definitions
  26 #define CPACR_TTA_EN            (1UL << 28)
  27 #define CPACR_FPEN_EL1          (1UL << 20)
  28 #define CPACR_FPEN_FULL         (3UL << 20)
  29 #define CPACR_CP_FULL_ACCESS    0x300000
  30
  31 // Coprocessor Trap Register (CPTR)
  32 #define AARCH64_CPTR_TFP        (1 << 10)
  33
  34 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
  35 #define AARCH64_PFR0_FP         (0xF << 16)
  36 #define AARCH64_PFR0_GIC        (0xF << 24)
  37
  38 // SCR - Secure Configuration Register definitions
  39 #define SCR_NS                  (1 << 0)
  40 #define SCR_IRQ                 (1 << 1)
  41 #define SCR_FIQ                 (1 << 2)
  42 #define SCR_EA                  (1 << 3)
  43 #define SCR_FW                  (1 << 4)
  44 #define SCR_AW                  (1 << 5)
  45
  46 // MIDR - Main ID Register definitions
  47 #define ARM_CPU_TYPE_SHIFT      4
  48 #define ARM_CPU_TYPE_MASK       0xFFF
  49 #define ARM_CPU_TYPE_AEMv8      0xD0F
  50 #define ARM_CPU_TYPE_A53        0xD03
  51 #define ARM_CPU_TYPE_A57        0xD07
  52 #define ARM_CPU_TYPE_A15        0xC0F
  53 #define ARM_CPU_TYPE_A9         0xC09
  54 #define ARM_CPU_TYPE_A7         0xC07
  55 #define ARM_CPU_TYPE_A5         0xC05
  56
  57 #define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )
  58 #define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  59
  60 // Hypervisor Configuration Register
  61 #define ARM_HCR_FMO       BIT3
  62 #define ARM_HCR_IMO       BIT4
  63 #define ARM_HCR_AMO       BIT5
  64 #define ARM_HCR_TSC       BIT19
  65 #define ARM_HCR_TGE       BIT27
  66
  67 // Exception Syndrome Register
  68 #define AARCH64_ESR_EC(Ecr)    ((0x3F << 26) & (Ecr))
  69 #define AARCH64_ESR_ISS(Ecr)   ((0x1FFFFFF) & (Ecr))
  70
  71 #define AARCH64_ESR_EC_SMC32   (0x13 << 26)
  72 #define AARCH64_ESR_EC_SMC64   (0x17 << 26)
  73
  74 // AArch64 Exception Level
  75 #define AARCH64_EL3       0xC
  76 #define AARCH64_EL2       0x8
  77 #define AARCH64_EL1       0x4
  78
  79 // Saved Program Status Register definitions
  80 #define SPSR_A                  BIT8
  81 #define SPSR_I                  BIT7
  82 #define SPSR_F                  BIT6
  83
  84 #define SPSR_AARCH32            BIT4
  85
  86 #define SPSR_AARCH32_MODE_USER  0x0
  87 #define SPSR_AARCH32_MODE_FIQ   0x1
  88 #define SPSR_AARCH32_MODE_IRQ   0x2
  89 #define SPSR_AARCH32_MODE_SVC   0x3
  90 #define SPSR_AARCH32_MODE_ABORT 0x7
  91 #define SPSR_AARCH32_MODE_UNDEF 0xB
  92 #define SPSR_AARCH32_MODE_SYS   0xF
  93
  94 // Counter-timer Hypervisor Control register definitions
  95 #define CNTHCTL_EL2_EL1PCTEN    BIT0
  96 #define CNTHCTL_EL2_EL1PCEN     BIT1
  97
  98 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
  99
 100 VOID
 101 EFIAPI
 102 ArmEnableSWPInstruction (
 103   VOID
 104   );
 105
 106 UINTN
 107 EFIAPI
 108 ArmReadCbar (
 109   VOID
 110   );
 111
 112 UINTN
 113 EFIAPI
 114 ArmReadTpidrurw (
 115   VOID
 116   );
 117
 118 VOID
 119 EFIAPI
 120 ArmWriteTpidrurw (
 121   UINTN Value
 122   );
 123
 124 UINTN
 125 EFIAPI
 126 ArmGetTCR (
 127   VOID
 128   );
 129
 130 VOID
 131 EFIAPI
 132 ArmSetTCR (
 133   UINTN Value
 134   );
 135
 136 UINTN
 137 EFIAPI
 138 ArmGetMAIR (
 139   VOID
 140   );
 141
 142 VOID
 143 EFIAPI
 144 ArmSetMAIR (
 145   UINTN Value
 146   );
 147
 148 VOID
 149 EFIAPI
 150 ArmDisableAlignmentCheck (
 151   VOID
 152   );
 153
 154 VOID
 155 EFIAPI
 156 ArmEnableAlignmentCheck (
 157   VOID
 158   );
 159
 160 VOID
 161 EFIAPI
 162 ArmDisableAllExceptions (
 163   VOID
 164   );
 165
 166 VOID
 167 ArmWriteHcr (
 168   IN UINTN Hcr
 169   );
 170
 171 UINTN
 172 ArmReadCurrentEL (
 173   VOID
 174   );
 175
 176 UINT64
 177 PageAttributeToGcdAttribute (
 178   IN UINT64 PageAttributes
 179   );
 180
 181 UINT64
 182 GcdAttributeToPageAttribute (
 183   IN UINT64 GcdAttributes
 184   );
 185
 186 UINTN
 187 ArmWriteCptr (
 188   IN  UINT64 Cptr
 189   );
 190
 191 #endif // __AARCH64_H__