ArmPkg/Include/Chipset/AArch64.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __AARCH64_H__
  17 #define __AARCH64_H__
  18
  19 #include <Chipset/AArch64Mmu.h>
  20
  21 // ARM Interrupt ID in Exception Table
  22 #define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_AARCH64_IRQ
  23
  24 // CPACR - Coprocessor Access Control Register definitions
  25 #define CPACR_TTA_EN            (1UL << 28)
  26 #define CPACR_FPEN_EL1          (1UL << 20)
  27 #define CPACR_FPEN_FULL         (3UL << 20)
  28 #define CPACR_CP_FULL_ACCESS    0x300000
  29
  30 // Coprocessor Trap Register (CPTR)
  31 #define AARCH64_CPTR_TFP        (1 << 10)
  32
  33 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
  34 #define AARCH64_PFR0_FP         (0xF << 16)
  35 #define AARCH64_PFR0_GIC        (0xF << 24)
  36
  37 // SCR - Secure Configuration Register definitions
  38 #define SCR_NS                  (1 << 0)
  39 #define SCR_IRQ                 (1 << 1)
  40 #define SCR_FIQ                 (1 << 2)
  41 #define SCR_EA                  (1 << 3)
  42 #define SCR_FW                  (1 << 4)
  43 #define SCR_AW                  (1 << 5)
  44
  45 // MIDR - Main ID Register definitions
  46 #define ARM_CPU_TYPE_SHIFT      4
  47 #define ARM_CPU_TYPE_MASK       0xFFF
  48 #define ARM_CPU_TYPE_AEMv8      0xD0F
  49 #define ARM_CPU_TYPE_A53        0xD03
  50 #define ARM_CPU_TYPE_A57        0xD07
  51 #define ARM_CPU_TYPE_A72        0xD08
  52 #define ARM_CPU_TYPE_A15        0xC0F
  53 #define ARM_CPU_TYPE_A9         0xC09
  54 #define ARM_CPU_TYPE_A7         0xC07
  55 #define ARM_CPU_TYPE_A5         0xC05
  56
  57 #define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )
  58 #define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  59
  60 // Hypervisor Configuration Register
  61 #define ARM_HCR_FMO       BIT3
  62 #define ARM_HCR_IMO       BIT4
  63 #define ARM_HCR_AMO       BIT5
  64 #define ARM_HCR_TSC       BIT19
  65 #define ARM_HCR_TGE       BIT27
  66
  67 // Exception Syndrome Register
  68 #define AARCH64_ESR_EC(Ecr)    ((0x3F << 26) & (Ecr))
  69 #define AARCH64_ESR_ISS(Ecr)   ((0x1FFFFFF) & (Ecr))
  70
  71 #define AARCH64_ESR_EC_SMC32   (0x13 << 26)
  72 #define AARCH64_ESR_EC_SMC64   (0x17 << 26)
  73
  74 // AArch64 Exception Level
  75 #define AARCH64_EL3       0xC
  76 #define AARCH64_EL2       0x8
  77 #define AARCH64_EL1       0x4
  78
  79 // Saved Program Status Register definitions
  80 #define SPSR_A                  BIT8
  81 #define SPSR_I                  BIT7
  82 #define SPSR_F                  BIT6
  83
  84 #define SPSR_AARCH32            BIT4
  85
  86 #define SPSR_AARCH32_MODE_USER  0x0
  87 #define SPSR_AARCH32_MODE_FIQ   0x1
  88 #define SPSR_AARCH32_MODE_IRQ   0x2
  89 #define SPSR_AARCH32_MODE_SVC   0x3
  90 #define SPSR_AARCH32_MODE_ABORT 0x7
  91 #define SPSR_AARCH32_MODE_UNDEF 0xB
  92 #define SPSR_AARCH32_MODE_SYS   0xF
  93
  94 // Counter-timer Hypervisor Control register definitions
  95 #define CNTHCTL_EL2_EL1PCTEN    BIT0
  96 #define CNTHCTL_EL2_EL1PCEN     BIT1
  97
  98 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
  99
 100 // Vector table offset definitions
 101 #define ARM_VECTOR_CUR_SP0_SYNC 0x000
 102 #define ARM_VECTOR_CUR_SP0_IRQ  0x080
 103 #define ARM_VECTOR_CUR_SP0_FIQ  0x100
 104 #define ARM_VECTOR_CUR_SP0_SERR 0x180
 105
 106 #define ARM_VECTOR_CUR_SPx_SYNC 0x200
 107 #define ARM_VECTOR_CUR_SPx_IRQ  0x280
 108 #define ARM_VECTOR_CUR_SPx_FIQ  0x300
 109 #define ARM_VECTOR_CUR_SPx_SERR 0x380
 110
 111 #define ARM_VECTOR_LOW_A64_SYNC 0x400
 112 #define ARM_VECTOR_LOW_A64_IRQ  0x480
 113 #define ARM_VECTOR_LOW_A64_FIQ  0x500
 114 #define ARM_VECTOR_LOW_A64_SERR 0x580
 115
 116 #define ARM_VECTOR_LOW_A32_SYNC 0x600
 117 #define ARM_VECTOR_LOW_A32_IRQ  0x680
 118 #define ARM_VECTOR_LOW_A32_FIQ  0x700
 119 #define ARM_VECTOR_LOW_A32_SERR 0x780
 120
 121 #define VECTOR_BASE(tbl)          \
 122   .section .text.##tbl##,"ax";    \
 123   .align 11;                      \
 124   .org 0x0;                       \
 125   GCC_ASM_EXPORT(tbl);            \
 126   ASM_PFX(tbl):                   \
 127
 128 #define VECTOR_ENTRY(tbl, off)    \
 129   .org off
 130
 131 #define VECTOR_END(tbl)           \
 132   .org 0x800;                     \
 133   .previous
 134
 135 VOID
 136 EFIAPI
 137 ArmEnableSWPInstruction (
 138   VOID
 139   );
 140
 141 UINTN
 142 EFIAPI
 143 ArmReadCbar (
 144   VOID
 145   );
 146
 147 UINTN
 148 EFIAPI
 149 ArmReadTpidrurw (
 150   VOID
 151   );
 152
 153 VOID
 154 EFIAPI
 155 ArmWriteTpidrurw (
 156   UINTN Value
 157   );
 158
 159 UINTN
 160 EFIAPI
 161 ArmGetTCR (
 162   VOID
 163   );
 164
 165 VOID
 166 EFIAPI
 167 ArmSetTCR (
 168   UINTN Value
 169   );
 170
 171 UINTN
 172 EFIAPI
 173 ArmGetMAIR (
 174   VOID
 175   );
 176
 177 VOID
 178 EFIAPI
 179 ArmSetMAIR (
 180   UINTN Value
 181   );
 182
 183 VOID
 184 EFIAPI
 185 ArmDisableAlignmentCheck (
 186   VOID
 187   );
 188
 189 VOID
 190 EFIAPI
 191 ArmEnableAlignmentCheck (
 192   VOID
 193   );
 194
 195 VOID
 196 EFIAPI
 197 ArmDisableStackAlignmentCheck (
 198   VOID
 199   );
 200
 201 VOID
 202 EFIAPI
 203 ArmEnableStackAlignmentCheck (
 204   VOID
 205   );
 206
 207 VOID
 208 EFIAPI
 209 ArmDisableAllExceptions (
 210   VOID
 211   );
 212
 213 VOID
 214 ArmWriteHcr (
 215   IN UINTN Hcr
 216   );
 217
 218 UINTN
 219 ArmReadHcr (
 220   VOID
 221   );
 222
 223 UINTN
 224 ArmReadCurrentEL (
 225   VOID
 226   );
 227
 228 UINT64
 229 PageAttributeToGcdAttribute (
 230   IN UINT64 PageAttributes
 231   );
 232
 233 UINTN
 234 ArmWriteCptr (
 235   IN  UINT64 Cptr
 236   );
 237
 238 UINT32
 239 ArmReadCntHctl (
 240   VOID
 241   );
 242
 243 VOID
 244 ArmWriteCntHctl (
 245   IN UINT32 CntHctl
 246   );
 247
 248 #endif // __AARCH64_H__