ArmPkg/Include/Chipset/AArch64.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __AARCH64_H__
  17 #define __AARCH64_H__
  18
  19 #include <Chipset/AArch64Mmu.h>
  20 #include <Chipset/ArmArchTimer.h>
  21
  22 // ARM Interrupt ID in Exception Table
  23 #define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_AARCH64_IRQ
  24
  25 // CPACR - Coprocessor Access Control Register definitions
  26 #define CPACR_TTA_EN            (1UL << 28)
  27 #define CPACR_FPEN_EL1          (1UL << 20)
  28 #define CPACR_FPEN_FULL         (3UL << 20)
  29 #define CPACR_CP_FULL_ACCESS    0x300000
  30
  31 // Coprocessor Trap Register (CPTR)
  32 #define AARCH64_CPTR_TFP        (1 << 10)
  33
  34 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
  35 #define AARCH64_PFR0_FP         (0xF << 16)
  36
  37 // NSACR - Non-Secure Access Control Register definitions
  38 #define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)
  39 #define NSACR_NSD32DIS          (1 << 14)
  40 #define NSACR_NSASEDIS          (1 << 15)
  41 #define NSACR_PLE               (1 << 16)
  42 #define NSACR_TL                (1 << 17)
  43 #define NSACR_NS_SMP            (1 << 18)
  44 #define NSACR_RFR               (1 << 19)
  45
  46 // SCR - Secure Configuration Register definitions
  47 #define SCR_NS                  (1 << 0)
  48 #define SCR_IRQ                 (1 << 1)
  49 #define SCR_FIQ                 (1 << 2)
  50 #define SCR_EA                  (1 << 3)
  51 #define SCR_FW                  (1 << 4)
  52 #define SCR_AW                  (1 << 5)
  53
  54 // MIDR - Main ID Register definitions
  55 #define ARM_CPU_TYPE_MASK       0xFFF
  56 #define ARM_CPU_TYPE_AEMv8      0xD0F
  57 #define ARM_CPU_TYPE_A15        0xC0F
  58 #define ARM_CPU_TYPE_A9         0xC09
  59 #define ARM_CPU_TYPE_A5         0xC05
  60
  61 // Hypervisor Configuration Register
  62 #define ARM_HCR_FMO                             BIT3
  63 #define ARM_HCR_IMO                             BIT4
  64 #define ARM_HCR_AMO                             BIT5
  65 #define ARM_HCR_TGE                             BIT27
  66
  67 // AArch64 Exception Level
  68 #define AARCH64_EL3       0xC
  69 #define AARCH64_EL2       0x8
  70 #define AARCH64_EL1       0x4
  71
  72 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
  73
  74 VOID
  75 EFIAPI
  76 ArmEnableSWPInstruction (
  77   VOID
  78   );
  79
  80 UINTN
  81 EFIAPI
  82 ArmReadCbar (
  83   VOID
  84   );
  85
  86 UINTN
  87 EFIAPI
  88 ArmReadTpidrurw (
  89   VOID
  90   );
  91
  92 VOID
  93 EFIAPI
  94 ArmWriteTpidrurw (
  95   UINTN Value
  96   );
  97
  98 UINTN
  99 EFIAPI
 100 ArmIsArchTimerImplemented (
 101   VOID
 102   );
 103
 104 UINTN
 105 EFIAPI
 106 ArmReadIdPfr0 (
 107   VOID
 108   );
 109
 110 UINTN
 111 EFIAPI
 112 ArmReadIdPfr1 (
 113   VOID
 114   );
 115
 116 UINTN
 117 EFIAPI
 118 ArmGetTCR (
 119   VOID
 120   );
 121
 122 VOID
 123 EFIAPI
 124 ArmSetTCR (
 125   UINTN Value
 126   );
 127
 128 UINTN
 129 EFIAPI
 130 ArmGetMAIR (
 131   VOID
 132   );
 133
 134 VOID
 135 EFIAPI
 136 ArmSetMAIR (
 137   UINTN Value
 138   );
 139
 140 VOID
 141 EFIAPI
 142 ArmDisableAlignmentCheck (
 143   VOID
 144   );
 145
 146
 147 VOID
 148 EFIAPI
 149 ArmEnableAlignmentCheck (
 150   VOID
 151   );
 152
 153 VOID
 154 EFIAPI
 155 ArmDisableAllExceptions (
 156   VOID
 157   );
 158
 159 VOID
 160 ArmWriteHcr (
 161   IN UINTN Hcr
 162   );
 163
 164 UINTN
 165 ArmReadCurrentEL (
 166   VOID
 167   );
 168
 169 UINT64
 170 PageAttributeToGcdAttribute (
 171   IN UINT64 PageAttributes
 172   );
 173
 174 UINT64
 175 GcdAttributeToPageAttribute (
 176   IN UINT64 GcdAttributes
 177   );
 178
 179 #endif // __AARCH64_H__