ArmPkg/Include/Chipset/AArch64.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __AARCH64_H__
  17 #define __AARCH64_H__
  18
  19 #include <Chipset/AArch64Mmu.h>
  20 #include <Chipset/ArmArchTimer.h>
  21
  22 // ARM Interrupt ID in Exception Table
  23 #define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_AARCH64_IRQ
  24
  25 // CPACR - Coprocessor Access Control Register definitions
  26 #define CPACR_TTA_EN            (1UL << 28)
  27 #define CPACR_FPEN_EL1          (1UL << 20)
  28 #define CPACR_FPEN_FULL         (3UL << 20)
  29 #define CPACR_CP_FULL_ACCESS    0x300000
  30
  31 // Coprocessor Trap Register (CPTR)
  32 #define AARCH64_CPTR_TFP        (1 << 10)
  33
  34 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
  35 #define AARCH64_PFR0_FP         (0xF << 16)
  36 #define AARCH64_PFR0_GIC        (0xF << 24)
  37
  38 // SCR - Secure Configuration Register definitions
  39 #define SCR_NS                  (1 << 0)
  40 #define SCR_IRQ                 (1 << 1)
  41 #define SCR_FIQ                 (1 << 2)
  42 #define SCR_EA                  (1 << 3)
  43 #define SCR_FW                  (1 << 4)
  44 #define SCR_AW                  (1 << 5)
  45
  46 // MIDR - Main ID Register definitions
  47 #define ARM_CPU_TYPE_MASK       0xFFF
  48 #define ARM_CPU_TYPE_AEMv8      0xD0F
  49 #define ARM_CPU_TYPE_A53        0xD03
  50 #define ARM_CPU_TYPE_A57        0xD07
  51 #define ARM_CPU_TYPE_A15        0xC0F
  52 #define ARM_CPU_TYPE_A9         0xC09
  53 #define ARM_CPU_TYPE_A5         0xC05
  54
  55 #define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )
  56 #define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  57
  58 // Hypervisor Configuration Register
  59 #define ARM_HCR_FMO       BIT3
  60 #define ARM_HCR_IMO       BIT4
  61 #define ARM_HCR_AMO       BIT5
  62 #define ARM_HCR_TSC       BIT19
  63 #define ARM_HCR_TGE       BIT27
  64
  65 // AArch64 Exception Level
  66 #define AARCH64_EL3       0xC
  67 #define AARCH64_EL2       0x8
  68 #define AARCH64_EL1       0x4
  69
  70 // Saved Program Status Register definitions
  71 #define SPSR_A                  BIT8
  72 #define SPSR_I                  BIT7
  73 #define SPSR_F                  BIT6
  74
  75 #define SPSR_AARCH32            BIT4
  76
  77 #define SPSR_AARCH32_MODE_USER  0x0
  78 #define SPSR_AARCH32_MODE_FIQ   0x1
  79 #define SPSR_AARCH32_MODE_IRQ   0x2
  80 #define SPSR_AARCH32_MODE_SVC   0x3
  81 #define SPSR_AARCH32_MODE_ABORT 0x7
  82 #define SPSR_AARCH32_MODE_UNDEF 0xB
  83 #define SPSR_AARCH32_MODE_SYS   0xF
  84
  85 // Counter-timer Hypervisor Control register definitions
  86 #define CNTHCTL_EL2_EL1PCTEN    BIT0
  87 #define CNTHCTL_EL2_EL1PCEN     BIT1
  88
  89 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
  90
  91 VOID
  92 EFIAPI
  93 ArmEnableSWPInstruction (
  94   VOID
  95   );
  96
  97 UINTN
  98 EFIAPI
  99 ArmReadCbar (
 100   VOID
 101   );
 102
 103 UINTN
 104 EFIAPI
 105 ArmReadTpidrurw (
 106   VOID
 107   );
 108
 109 VOID
 110 EFIAPI
 111 ArmWriteTpidrurw (
 112   UINTN Value
 113   );
 114
 115 UINTN
 116 EFIAPI
 117 ArmGetTCR (
 118   VOID
 119   );
 120
 121 VOID
 122 EFIAPI
 123 ArmSetTCR (
 124   UINTN Value
 125   );
 126
 127 UINTN
 128 EFIAPI
 129 ArmGetMAIR (
 130   VOID
 131   );
 132
 133 VOID
 134 EFIAPI
 135 ArmSetMAIR (
 136   UINTN Value
 137   );
 138
 139 VOID
 140 EFIAPI
 141 ArmDisableAlignmentCheck (
 142   VOID
 143   );
 144
 145 VOID
 146 EFIAPI
 147 ArmEnableAlignmentCheck (
 148   VOID
 149   );
 150
 151 VOID
 152 EFIAPI
 153 ArmDisableAllExceptions (
 154   VOID
 155   );
 156
 157 VOID
 158 ArmWriteHcr (
 159   IN UINTN Hcr
 160   );
 161
 162 UINTN
 163 ArmReadCurrentEL (
 164   VOID
 165   );
 166
 167 UINT64
 168 PageAttributeToGcdAttribute (
 169   IN UINT64 PageAttributes
 170   );
 171
 172 UINT64
 173 GcdAttributeToPageAttribute (
 174   IN UINT64 GcdAttributes
 175   );
 176
 177 UINTN
 178 ArmWriteCptr (
 179   IN  UINT64 Cptr
 180   );
 181
 182 #endif // __AARCH64_H__