ArmPkg/Include/Chipset/AArch64Mmu.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
   4 *
   5 *  SPDX-License-Identifier: BSD-2-Clause-Patent
   6 *
   7 **/
   8
   9 #ifndef AARCH64_MMU_H_
  10 #define AARCH64_MMU_H_
  11
  12 //
  13 // Memory Attribute Indirection register Definitions
  14 //
  15 #define MAIR_ATTR_DEVICE_MEMORY                0x0ULL
  16 #define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE  0x44ULL
  17 #define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH  0xBBULL
  18 #define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK     0xFFULL
  19
  20 #define MAIR_ATTR(n, value)  ((value) << (((n) >> 2)*8))
  21
  22 //
  23 // Long-descriptor Translation Table format
  24 //
  25
  26 // Return the smallest offset from the table level.
  27 // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
  28 #define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel)  (12 + ((3 - (TableLevel)) * 9))
  29
  30 #define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level)  (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
  31
  32 // Get the associated entry in the given Translation Table
  33 #define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address)  \
  34     ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))
  35
  36 // Return the smallest address granularity from the table level.
  37 // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
  38 #define TT_ADDRESS_AT_LEVEL(TableLevel)  (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
  39
  40 #define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \
  41     ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))
  42
  43 // There are 512 entries per table when 4K Granularity
  44 #define TT_ENTRY_COUNT                  512
  45 #define TT_ALIGNMENT_BLOCK_ENTRY        BIT12
  46 #define TT_ALIGNMENT_DESCRIPTION_TABLE  BIT12
  47
  48 #define TT_ADDRESS_MASK_BLOCK_ENTRY        (0xFFFFFFFFFULL << 12)
  49 #define TT_ADDRESS_MASK_DESCRIPTION_TABLE  (0xFFFFFFFFFULL << 12)
  50
  51 #define TT_TYPE_MASK                0x3
  52 #define TT_TYPE_TABLE_ENTRY         0x3
  53 #define TT_TYPE_BLOCK_ENTRY         0x1
  54 #define TT_TYPE_BLOCK_ENTRY_LEVEL3  0x3
  55
  56 #define TT_ATTR_INDX_MASK                  (0x7 << 2)
  57 #define TT_ATTR_INDX_DEVICE_MEMORY         (0x0 << 2)
  58 #define TT_ATTR_INDX_MEMORY_NON_CACHEABLE  (0x1 << 2)
  59 #define TT_ATTR_INDX_MEMORY_WRITE_THROUGH  (0x2 << 2)
  60 #define TT_ATTR_INDX_MEMORY_WRITE_BACK     (0x3 << 2)
  61
  62 #define TT_AP_MASK   (0x3UL << 6)
  63 #define TT_AP_NO_RW  (0x0UL << 6)
  64 #define TT_AP_RW_RW  (0x1UL << 6)
  65 #define TT_AP_NO_RO  (0x2UL << 6)
  66 #define TT_AP_RO_RO  (0x3UL << 6)
  67
  68 #define TT_NS  BIT5
  69 #define TT_AF  BIT10
  70
  71 #define TT_SH_NON_SHAREABLE    (0x0 << 8)
  72 #define TT_SH_OUTER_SHAREABLE  (0x2 << 8)
  73 #define TT_SH_INNER_SHAREABLE  (0x3 << 8)
  74 #define TT_SH_MASK             (0x3 << 8)
  75
  76 #define TT_PXN_MASK  BIT53
  77 #define TT_UXN_MASK  BIT54                              // EL1&0
  78 #define TT_XN_MASK   BIT54                              // EL2 / EL3
  79
  80 #define TT_ATTRIBUTES_MASK  ((0xFFFULL << 52) | (0x3FFULL << 2))
  81
  82 #define TT_TABLE_PXN  BIT59
  83 #define TT_TABLE_UXN  BIT60                             // EL1&0
  84 #define TT_TABLE_XN   BIT60                             // EL2 / EL3
  85 #define TT_TABLE_NS   BIT63
  86
  87 #define TT_TABLE_AP_MASK             (BIT62 | BIT61)
  88 #define TT_TABLE_AP_NO_PERMISSION    (0x0ULL << 61)
  89 #define TT_TABLE_AP_EL0_NO_ACCESS    (0x1ULL << 61)
  90 #define TT_TABLE_AP_NO_WRITE_ACCESS  (0x2ULL << 61)
  91
  92 //
  93 // Translation Control Register
  94 //
  95 #define TCR_T0SZ_MASK  0x3FUL
  96
  97 #define TCR_PS_4GB    (0UL << 16)
  98 #define TCR_PS_64GB   (1UL << 16)
  99 #define TCR_PS_1TB    (2UL << 16)
 100 #define TCR_PS_4TB    (3UL << 16)
 101 #define TCR_PS_16TB   (4UL << 16)
 102 #define TCR_PS_256TB  (5UL << 16)
 103
 104 #define TCR_TG0_4KB  (0UL << 14)
 105 #define TCR_TG1_4KB  (2UL << 30)
 106
 107 #define TCR_IPS_4GB    (0ULL << 32)
 108 #define TCR_IPS_64GB   (1ULL << 32)
 109 #define TCR_IPS_1TB    (2ULL << 32)
 110 #define TCR_IPS_4TB    (3ULL << 32)
 111 #define TCR_IPS_16TB   (4ULL << 32)
 112 #define TCR_IPS_256TB  (5ULL << 32)
 113
 114 #define TCR_EPD1  (1UL << 23)
 115
 116 #define TTBR_ASID_FIELD  (48)
 117 #define TTBR_ASID_MASK   (0xFF << TTBR_ASID_FIELD)
 118 #define TTBR_BADDR_MASK  (0xFFFFFFFFFFFF )                     // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits
 119
 120 #define TCR_EL1_T0SZ_FIELD   (0)
 121 #define TCR_EL1_EPD0_FIELD   (7)
 122 #define TCR_EL1_IRGN0_FIELD  (8)
 123 #define TCR_EL1_ORGN0_FIELD  (10)
 124 #define TCR_EL1_SH0_FIELD    (12)
 125 #define TCR_EL1_TG0_FIELD    (14)
 126 #define TCR_EL1_T1SZ_FIELD   (16)
 127 #define TCR_EL1_A1_FIELD     (22)
 128 #define TCR_EL1_EPD1_FIELD   (23)
 129 #define TCR_EL1_IRGN1_FIELD  (24)
 130 #define TCR_EL1_ORGN1_FIELD  (26)
 131 #define TCR_EL1_SH1_FIELD    (28)
 132 #define TCR_EL1_TG1_FIELD    (30)
 133 #define TCR_EL1_IPS_FIELD    (32)
 134 #define TCR_EL1_AS_FIELD     (36)
 135 #define TCR_EL1_TBI0_FIELD   (37)
 136 #define TCR_EL1_TBI1_FIELD   (38)
 137 #define TCR_EL1_T0SZ_MASK    (0x1FUL << TCR_EL1_T0SZ_FIELD)
 138 #define TCR_EL1_EPD0_MASK    (0x01UL << TCR_EL1_EPD0_FIELD)
 139 #define TCR_EL1_IRGN0_MASK   (0x03UL << TCR_EL1_IRGN0_FIELD)
 140 #define TCR_EL1_ORGN0_MASK   (0x03UL << TCR_EL1_ORGN0_FIELD)
 141 #define TCR_EL1_SH0_MASK     (0x03UL << TCR_EL1_SH0_FIELD)
 142 #define TCR_EL1_TG0_MASK     (0x01UL << TCR_EL1_TG0_FIELD)
 143 #define TCR_EL1_T1SZ_MASK    (0x1FUL << TCR_EL1_T1SZ_FIELD)
 144 #define TCR_EL1_A1_MASK      (0x01UL << TCR_EL1_A1_FIELD)
 145 #define TCR_EL1_EPD1_MASK    (0x01UL << TCR_EL1_EPD1_FIELD)
 146 #define TCR_EL1_IRGN1_MASK   (0x03UL << TCR_EL1_IRGN1_FIELD)
 147 #define TCR_EL1_ORGN1_MASK   (0x03UL << TCR_EL1_ORGN1_FIELD)
 148 #define TCR_EL1_SH1_MASK     (0x03UL << TCR_EL1_SH1_FIELD)
 149 #define TCR_EL1_TG1_MASK     (0x01UL << TCR_EL1_TG1_FIELD)
 150 #define TCR_EL1_IPS_MASK     (0x07UL << TCR_EL1_IPS_FIELD)
 151 #define TCR_EL1_AS_MASK      (0x01UL << TCR_EL1_AS_FIELD)
 152 #define TCR_EL1_TBI0_MASK    (0x01UL << TCR_EL1_TBI0_FIELD)
 153 #define TCR_EL1_TBI1_MASK    (0x01UL << TCR_EL1_TBI1_FIELD)
 154
 155 #define TCR_EL23_T0SZ_FIELD   (0)
 156 #define TCR_EL23_IRGN0_FIELD  (8)
 157 #define TCR_EL23_ORGN0_FIELD  (10)
 158 #define TCR_EL23_SH0_FIELD    (12)
 159 #define TCR_EL23_TG0_FIELD    (14)
 160 #define TCR_EL23_PS_FIELD     (16)
 161 #define TCR_EL23_T0SZ_MASK    (0x1FUL << TCR_EL23_T0SZ_FIELD)
 162 #define TCR_EL23_IRGN0_MASK   (0x03UL << TCR_EL23_IRGN0_FIELD)
 163 #define TCR_EL23_ORGN0_MASK   (0x03UL << TCR_EL23_ORGN0_FIELD)
 164 #define TCR_EL23_SH0_MASK     (0x03UL << TCR_EL23_SH0_FIELD)
 165 #define TCR_EL23_TG0_MASK     (0x01UL << TCR_EL23_TG0_FIELD)
 166 #define TCR_EL23_PS_MASK      (0x07UL << TCR_EL23_PS_FIELD)
 167
 168 #define TCR_RGN_OUTER_NON_CACHEABLE        (0x0UL << 10)
 169 #define TCR_RGN_OUTER_WRITE_BACK_ALLOC     (0x1UL << 10)
 170 #define TCR_RGN_OUTER_WRITE_THROUGH        (0x2UL << 10)
 171 #define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC  (0x3UL << 10)
 172
 173 #define TCR_RGN_INNER_NON_CACHEABLE        (0x0UL << 8)
 174 #define TCR_RGN_INNER_WRITE_BACK_ALLOC     (0x1UL << 8)
 175 #define TCR_RGN_INNER_WRITE_THROUGH        (0x2UL << 8)
 176 #define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC  (0x3UL << 8)
 177
 178 #define TCR_SH_NON_SHAREABLE    (0x0UL << 12)
 179 #define TCR_SH_OUTER_SHAREABLE  (0x2UL << 12)
 180 #define TCR_SH_INNER_SHAREABLE  (0x3UL << 12)
 181
 182 #define TCR_PASZ_32BITS_4GB    (0x0UL)
 183 #define TCR_PASZ_36BITS_64GB   (0x1UL)
 184 #define TCR_PASZ_40BITS_1TB    (0x2UL)
 185 #define TCR_PASZ_42BITS_4TB    (0x3UL)
 186 #define TCR_PASZ_44BITS_16TB   (0x4UL)
 187 #define TCR_PASZ_48BITS_256TB  (0x5UL)
 188
 189 // The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
 190 // Virtual address range for 512GB of virtual space sets T*SZ to 25
 191 #define INPUT_ADDRESS_SIZE_TO_TXSZ(a)  (64 - a)
 192
 193 // Uses LPAE Page Table format
 194
 195 #endif // AARCH64_MMU_H_