ArmPkg/Include/Chipset/ArmV7.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef ARM_V7_H_
  11 #define ARM_V7_H_
  12
  13 #include <Chipset/ArmV7Mmu.h>
  14
  15 // ARM Interrupt ID in Exception Table
  16 #define ARM_ARCH_EXCEPTION_IRQ  EXCEPT_ARM_IRQ
  17
  18 // ID_PFR1 - ARM Processor Feature Register 1 definitions
  19 #define ARM_PFR1_SEC    (0xFUL << 4)
  20 #define ARM_PFR1_TIMER  (0xFUL << 16)
  21 #define ARM_PFR1_GIC    (0xFUL << 28)
  22
  23 // Domain Access Control Register
  24 #define DOMAIN_ACCESS_CONTROL_MASK(a)      (3UL << (2 * (a)))
  25 #define DOMAIN_ACCESS_CONTROL_NONE(a)      (0UL << (2 * (a)))
  26 #define DOMAIN_ACCESS_CONTROL_CLIENT(a)    (1UL << (2 * (a)))
  27 #define DOMAIN_ACCESS_CONTROL_RESERVED(a)  (2UL << (2 * (a)))
  28 #define DOMAIN_ACCESS_CONTROL_MANAGER(a)   (3UL << (2 * (a)))
  29
  30 // CPSR - Coprocessor Status Register definitions
  31 #define CPSR_MODE_USER       0x10
  32 #define CPSR_MODE_FIQ        0x11
  33 #define CPSR_MODE_IRQ        0x12
  34 #define CPSR_MODE_SVC        0x13
  35 #define CPSR_MODE_ABORT      0x17
  36 #define CPSR_MODE_HYP        0x1A
  37 #define CPSR_MODE_UNDEFINED  0x1B
  38 #define CPSR_MODE_SYSTEM     0x1F
  39 #define CPSR_MODE_MASK       0x1F
  40 #define CPSR_ASYNC_ABORT     (1 << 8)
  41 #define CPSR_IRQ             (1 << 7)
  42 #define CPSR_FIQ             (1 << 6)
  43
  44 // CPACR - Coprocessor Access Control Register definitions
  45 #define CPACR_CP_DENIED(cp)  0x00
  46 #define CPACR_CP_PRIV(cp)    ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
  47 #define CPACR_CP_FULL(cp)    ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
  48 #define CPACR_ASEDIS          (1 << 31)
  49 #define CPACR_D32DIS          (1 << 30)
  50 #define CPACR_CP_FULL_ACCESS  0x0FFFFFFF
  51
  52 // NSACR - Non-Secure Access Control Register definitions
  53 #define NSACR_CP(cp)  ((1 << (cp)) & 0x3FFF)
  54 #define NSACR_NSD32DIS  (1 << 14)
  55 #define NSACR_NSASEDIS  (1 << 15)
  56 #define NSACR_PLE       (1 << 16)
  57 #define NSACR_TL        (1 << 17)
  58 #define NSACR_NS_SMP    (1 << 18)
  59 #define NSACR_RFR       (1 << 19)
  60
  61 // SCR - Secure Configuration Register definitions
  62 #define SCR_NS   (1 << 0)
  63 #define SCR_IRQ  (1 << 1)
  64 #define SCR_FIQ  (1 << 2)
  65 #define SCR_EA   (1 << 3)
  66 #define SCR_FW   (1 << 4)
  67 #define SCR_AW   (1 << 5)
  68
  69 // MIDR - Main ID Register definitions
  70 #define ARM_CPU_TYPE_SHIFT  4
  71 #define ARM_CPU_TYPE_MASK   0xFFF
  72 #define ARM_CPU_TYPE_AEMV8  0xD0F
  73 #define ARM_CPU_TYPE_A53    0xD03
  74 #define ARM_CPU_TYPE_A57    0xD07
  75 #define ARM_CPU_TYPE_A15    0xC0F
  76 #define ARM_CPU_TYPE_A12    0xC0D
  77 #define ARM_CPU_TYPE_A9     0xC09
  78 #define ARM_CPU_TYPE_A7     0xC07
  79 #define ARM_CPU_TYPE_A5     0xC05
  80
  81 #define ARM_CPU_REV_MASK  ((0xF << 20) | (0xF) )
  82 #define ARM_CPU_REV(rn, pn)  ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  83
  84 #define ARM_VECTOR_TABLE_ALIGNMENT  ((1 << 5)-1)
  85
  86 VOID
  87 EFIAPI
  88 ArmEnableSWPInstruction (
  89   VOID
  90   );
  91
  92 UINTN
  93 EFIAPI
  94 ArmReadCbar (
  95   VOID
  96   );
  97
  98 UINTN
  99 EFIAPI
 100 ArmReadTpidrurw (
 101   VOID
 102   );
 103
 104 VOID
 105 EFIAPI
 106 ArmWriteTpidrurw (
 107   UINTN  Value
 108   );
 109
 110 UINT32
 111 EFIAPI
 112 ArmReadNsacr (
 113   VOID
 114   );
 115
 116 VOID
 117 EFIAPI
 118 ArmWriteNsacr (
 119   IN  UINT32  Nsacr
 120   );
 121
 122 #endif // ARM_V7_H_