ArmPkg/Include/Chipset/ArmV7.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_V7_H__
  17 #define __ARM_V7_H__
  18
  19 #include <Chipset/ArmV7Mmu.h>
  20 #include <Chipset/ArmV7ArchTimer.h>
  21
  22 // Domain Access Control Register
  23 #define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))
  24 #define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))
  25 #define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))
  26 #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
  27 #define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))
  28
  29 // CPACR - Coprocessor Access Control Register definitions
  30 #define CPACR_CP_DENIED(cp)     0x00
  31 #define CPACR_CP_PRIV(cp)       ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
  32 #define CPACR_CP_FULL(cp)       ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
  33 #define CPACR_ASEDIS            (1 << 31)
  34 #define CPACR_D32DIS            (1 << 30)
  35 #define CPACR_CP_FULL_ACCESS    0x0FFFFFFF
  36
  37 // NSACR - Non-Secure Access Control Register definitions
  38 #define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)
  39 #define NSACR_NSD32DIS          (1 << 14)
  40 #define NSACR_NSASEDIS          (1 << 15)
  41 #define NSACR_PLE               (1 << 16)
  42 #define NSACR_TL                (1 << 17)
  43 #define NSACR_NS_SMP            (1 << 18)
  44 #define NSACR_RFR               (1 << 19)
  45
  46 // SCR - Secure Configuration Register definitions
  47 #define SCR_NS                  (1 << 0)
  48 #define SCR_IRQ                 (1 << 1)
  49 #define SCR_FIQ                 (1 << 2)
  50 #define SCR_EA                  (1 << 3)
  51 #define SCR_FW                  (1 << 4)
  52 #define SCR_AW                  (1 << 5)
  53
  54 // MIDR - Main ID Register definitions
  55 #define ARM_CPU_TYPE_MASK       0xFFF
  56 #define ARM_CPU_TYPE_A15        0xC0F
  57 #define ARM_CPU_TYPE_A9         0xC09
  58 #define ARM_CPU_TYPE_A5         0xC05
  59
  60 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
  61
  62 VOID
  63 EFIAPI
  64 ArmEnableSWPInstruction (
  65   VOID
  66   );
  67
  68 UINTN
  69 EFIAPI
  70 ArmReadCbar (
  71   VOID
  72   );
  73
  74 UINTN
  75 EFIAPI
  76 ArmReadTpidrurw (
  77   VOID
  78   );
  79
  80 VOID
  81 EFIAPI
  82 ArmWriteTpidrurw (
  83   UINTN Value
  84   );
  85
  86 UINTN
  87 EFIAPI
  88 ArmIsArchTimerImplemented (
  89   VOID
  90   );
  91
  92 UINTN
  93 EFIAPI
  94 ArmReadIdPfr1 (
  95   VOID
  96   );
  97
  98 #endif // __ARM_V7_H__